What is a Block RAM in an FPGA?

[Music] let's talk about block rims block gram is a discrete part of an FPGA used to store data and this video is going to discuss lots of details about where they might be used how they're used so what's going to do it block Rams when might a block Ram be used or Bram for short in general storing data so for example large look-up tables like a lookup table that converts Celsius to Fahrenheit where you're given a Celsius value you want to look at what the Fahrenheit value is for that particular Celsius input you can use a lookup table for that given some X what's the lie that's a lookup table storing read-only data like some maybe you have some calibration parameters for your design that get written only by the FPGA bitstream programming the block Ram and they get read by your design to calibrate some sensor for example you might be using a block Ram to store data off of some external device like an analog digital converter or a flash maybe you do some filtering on that analog digital converter and you need to store some data some history to do the filter that's a pretty common way to do it maybe you have a FIFO a FIFO is the first in first out data storage basically it's like a buffer may be storing some temporary data type those are always used for temporary data this is extremely common in video applications so storing one row of incoming video data to buffer it up is a very common usage for block grams in that situation it's usually used to cross clock domains which I'm going to talk about there's a next bullet counseling clock domains inside of a fight inside of an FPGA using a FIFO is a very common use for block grams this is extremely important and that's the details of cut across a clock domain is for another video but in general all these things are just ways to store large amounts of data so what is the block Ram it's a discrete part of your FPGA just like look-up tables and stirrers are discrete parts of your FPGA each FPGA has a limited discreet number of block Rams available to you and the way to find out how many you have is to go to your website for your particular FPGA you're using and then look under something that says like embedded Ram bits something to that effect so this FPGA the HX one that K from lattice has 64 K block Ram bits the HX or K has a TK F block Ram bits a little bit more there the thing you need to know here is it tells you the total amount of RAM bits but each individual block Ram has some amount of storage so in the lattice chips it's a 4 therefore K block Rams so there's a discrete so 64 divided by 4 is how many total block Rams there are how many discrete block Rams there are on this particular FPGA and that's important to know you can't use individual bits of a block Ram in different parts of your design you have to use the whole thing all at once and I'll get into a little bit more details about that most block Rams can be initialized to nonzero values on the FPGA initialization so when the FPGA comes up gets loaded from the bit stream most FPGAs can be aja lies to something non zero which is useful for the ROM application the read-only memory that I discussed previously one exception is micro semi because of the way that the FPGA is are designed those are unable to be pre-loaded there's a lot of configuration options for block Rams so there's single port dual port and FIFO those are the three most common and I'm going to discuss each one of those how they're the same how they're different in general though if you look at the picture over here block ramp has some width and some depth and if you multiply width times depth you're going to get either 4k 8 K 16 K or 32 K are the most common block ramp sizes usually 16 K is fairly common from for most FPGAs but the bigger ones today are don't a 32 maybe even 64 some smaller FPGA is like the one on the name line go board is a 4k block Ram but the thing is is that you need to remember that you always need to multiply width width by depth to get one of these numbers you can't divide the block Ram in half but rarely so pretty commonly you'll see widths that are like one bit wide two bits the wit needs to be a base to number so one bit wide two bit wide four bit why 8 16 32 64 maybe even 128 but that's rare rare now most of the time it's something like 16 bits wide by whatever the 4k / 16 deep okay so those different inches configurations for block grams there's a single port configuration in general block grams have two ports port a import B's what they're commonly referred to as and they have the same signals on both sides on a single port configuration port B is not used at all so you're only reading and writing from port a you know your report a could be in a ROM application read-only in which case right enables that were used it could be a readwrite application whatever it is these are the most common signals there are other signals on a block Ram but these are the ones that are most important to understand so block Rams are synchronous pieces of logic synchronous means that they're driven by a clock so clock is critical to having a block Ram some block Williams have a reset input most do actually that can reset them back to some initial zero condition there's a write an able signal when this is high whatever data is on this write data synchronous to the clock will be written at that particular address you get all that so address tells you where in the block Ram at what index to read or write to when you have write enable high so I want to write something it'll clock the data into the block Ram on the rising edge of the clock whatever data is in this write data input when write enable is low the block Ram will always just read out on to the read data output whatever address you get it so if you just set address to zero it will always just be reading from address space 0 of your block Ram continuously and that's okay there's really no negative there's no reason not to have it do that you just can ignore the data if you don't really care about it so that's the single port configuration that's the simplest one dual port block ramp configuration is when there are two clocks port a in port B are both going to be used and so that might be for example if you're if you're writing data on Forte on the same clocks that you're reading data off of port B that might be a configuration in which you need to use two ports instead of just one you know on a single port configuration you obviously can't read and write on the same clock cycle because you can only read or write at one time a single so a dual port configuration you can read on one clock cycle write on the same clock cycle write read so that might be a situation which you need to use a dual port configuration the thing to note about dual port configuration is that the clocks can be the same or they can be different so this is the way the best way in your design to cross clock domains with large amounts of data is to use a block Ram to act between the two clock domains because caught because block Rams are specifically designed to work across different clock domains so this clock a is running at clock on four days running at 50 megahertz and clock at 4 P is running at 670 megahertz that's okay the BOK Ram will actually handle that if on a normal conditions if you try to just clock data from one domain to another domain you can get problems metastability problems which is another topic for a different video so block Rams are a great way to control the flow across clock domains for this reason here is that there's two ports each with their own set of wires running at their own set of frequencies you can never write to the same address at the same time from both ports because there's going to be contention there so that's one thing you definitely want to avoid and also there's there are some problems one little like knit can be if you write to the address and you read from the address on the same clock cycle which data gets there first and that actually depends on the individual FPGA that you're using so just one little thing to be careful about not super common now and the last configuration that block Rams can be set up in is a Scifo configuration which again is a first-in first-out and this is extremely common for block Rams to be set up as psychos and fight foes generally have two it's the same signals but they're kind of called different things when it's a psycho configuration instead of port a import B there's a right side and a read side instead of right enable its I call it right big DV or right data valid so that's a pulse that's synchronous to the clock that tells the block Ram when to look at this right data input and register it into the block Ram fabric the new signals here are these four at the bottom full almost full empty and almost empty full and almost full are on the right side so the the data that's being shoved into your fly so so eiffel can be thought of it's like a tunnel driving through a tunnel so this is people two cars driving into the tunnel cars driving out of the tunnel two rules five those are for a different topic I have a different video I believe they're complicated with us to talk about them separately so I won't get into too many details about how cells work but two basic rules of the FIFO never right to a full FIFO never read from an empty FIFO if you obey those two rules you're going to be great another video coming about sine so so stay tuned for that so those are the main reasons why how you use a block Ram how specifically you would code to create block grams there's three main ways to do it they can be instantiated instantiating means the way you instantiate a sub-module in your code you can is going to create a blocker in the exact same way and most of the user guides for the individual vendors FPGA vendors will tell you how to instantiate it so there's usually a user guide that tells your memory memory usage guide and this will really you should definitely read this entire thing so to finish if you have never used block grams before because there's a lot of details in here about how they work so I highly recommend you go look at you know for whatever FPGA you're using look at the memory usage guide for it and then try to read through it carefully and understand block rims this video should give you a high enough overview so that you feel like you understand what this thing is talking about before you get started but this is still important to read through so here's an example of a Verilog instantiation of a 256 deep by 16 wide block Ram and this just shows you how you wire it up in the dialog and here's some initialization stuff that you can do as well and every vendor will have this type of information on the datasheet so that's the first way instantiation I like to instantiate block Rams personally under the get with one caveat which is that you need to create a wrapper around them it's a little bit more advanced but if you can create wrappers around instantiated block grams you can make them very dynamic kind of nice you can infer block Rams infer inference means that you write VHDL or Verilog code that describes the block Ram but you don't specifically tell the tools please put a blocker in here the tools will say I think what he wants to do is you want to put a block ramp here and they'll go infer that and put one down for you I do recommend this way once you're comfortable with black rims I think this is probably the best way to do it each user guide will tell you the recommended way for their particular synthesis tool to ensure block grams the best so for example for the lattice if you scroll down to the bottom of the memory usage guide there's this section here and so standard HDL code references so here's what a single port land looks like if you want to infer it you can just copy and paste this into your code so that's pretty handy there here's the HDL clears dual port ram here barrel log dual port ram VHDL same thing and the third way for most FPGA companies is you can use their their GUI to create them this is good for beginners so if you've never used block Rams before and you want to just like get click through the tool and see all the different ways you can customize them I think this is a good way to do it you should try to try playing with this my reason I'm hesitant for people who do large designs or advanced FPGA folks is that I have personally worked with designs where you can the issue with creating them via the GUI is that you create one block ram with one dip one width and one depth so if I need a 16 K wide by 256 deep I created once and I've stored in some file Oh and now I need eight wide by 512 deep I got to create that one so now I need four wide by 1024 deep I got to create that one separately and so you get it up in this situation where you're just creating these block Rams over and over again to solve to solve different situations which you might need them and that becomes tedious to keep track of it so for very large designs I don't recommend this method but for small design just check in and out it's fun so that takes care of block Rams read the memory usage guide for whatever FPGA you're working with if you don't yet have an FPGA to work with I recommend buying the go board on at namland comm they're available today for sale and it's the best way to keep me making these videos the more go boards that I'm able to sell the more videos I'm able to create so the better the whole system gets so please support this YouTube channel and get yourself a go board today thanks

Channel: nandland

Views: 60,742

Rating: 4.9478712 out of 5

Keywords: Block RAM, BRAM, FPGA, RAM, VHDL, Verilog, FIFO

Id: fqUuvwl4QJA

Length: 14min 59sec (899 seconds)

Published: Sun Apr 23 2017