What is a Flip-Flop? How are they used in FPGAs?

hello and welcome to another NAND landcom youtube tutorial in this video I'm going to talk about the second most important component inside of an FPGA and that is the flip-flop dented and we need some epic music here whip very important component side of an FPGA in the previous video I talked about look-up tables or less I told you how what's can be used to program any boolean algebra equation you can think of given three inputs or four inputs or five inputs and flip-flops are the second most important part of an FPGA and those are used in combination with lots to do everything as that of an FPGA for the most part there are other things inside of an FPGA but flip-flops and let's are by far the most important parts without them you would not have an FPGA so let's get into what is a flip-flop a foot plop can sometimes also be called a register but I'm going to draw what a flip-flop looks like now a flip-flop looks like this like there should be some epic music playing this is very exciting stuff so a flip-flop has two inputs and one output this right here is a D flip-flop that's what it is called there are other flip-flops there's a JK flip-flop for example T flip-flops I think are still things honestly I don't remember what the other ones are because they're not important if you're in if you're in an electronics class at college university you might be learning about other types of flip-flops I'll tell you that in the real world I'd be surprised if you ever use any of them other than a D flip-flop D flip-flops are butter inside FPGAs they are used by far the most frequently there are other inputs to flip-flops too by the way but for this video I'm just going to focus on these three inputs here there's a reset input for example but let's ignore that let's just talk about these three so D D is your is your data input arrow Dealey clock Q now so doesn't seem all that complicated there's just three things hmm what is a clock I have not introduced what a clock is so I suppose now is as good a time as any to introduce the concept of a clock clocks clocks inside of FPGAs I'm not talking about the wristwatch I'm not talking about an analog clock I am talking about a clock that looks like this o'clock is a square wave that it runs throughout your FPGA at some specified frequency frequency means cycles per second number of cycles per second so for example if you had a one mega Hertz clock that means mega is ten to the sixth power so one times ten to the sixth Hertz if you're unfamiliar with the concept of Hertz its cycles per second so cycles in this case a cycle in a clock is referring to the entire duration the entire action of a clock so it starts we can look at one cycle starting here going here here to the back down here so this is one clock cycle here so here's one clock cycle here's the second clock cycle here's the third clock cycle here is the fourth clock cycle cycles per second one mega Hertz meaning 1 million cycles per second so one megahertz clock is a clock that your FPGA might have might have 10 megahertz clock hundred megahertz clock FPGA is generally run around 100 megahertz clock frequency they can certainly run slower than that when you start getting faster than that you start to push the envelope for what the technology is capable of but clock is the is the fundamental part of what makes an FPGA tick and the reason for that is that it's the input to all your flip-flops all flip-flops have a clock input and the clock is the thing that drives the FPGA it is the most important thing to understand it and it's a little bit abstract to think about because they only exist inside FPGAs they don't exist a clock concept in this way does not exist inside of a processor a clock inside of a processor keeps things running but it doesn't go to every single flip-flop like it doesn't met feet every flip-flop has the clock so let's talk about it a little bit more since it is so important I kind of think of a clock as this giant gear that that rotates it almost got to make sense because it looks like teeth on a gear but in order for your flip-flops to actually turn and do stuff they need to have this clock running through them and turning the whole FPGA to FPGA moves as if it's sets of gears so you can think of it that way maybe that helps the clock for your FPGA is the main gear driving all of these little tiny flip-flops of which there are thousands tens of thousands sometimes hundreds of thousands of flip-flops inside one FPGA so now it's an abstract concept and it's going to take some time to understand how a clock works but I'm going to show you some waveforms that at first glance won't make a lot of sense but the more you get familiar with the concept the more it will make sense it is something that's going to take some practice on your end so I recommend looking at some more examples and and just just working through it eventually it becomes second nature but I'm going to show you the waveforms for a a D flip-flop so this is what it looks like I'm gonna race it so what happens previously I have shown in other videos what happens to your output given sets of inputs and they were pretty obvious with a lot you had or gates you had an gates that made up that were inside of the lookup table and it was pretty obvious when your input was a 1 you output was this when your when your input was 0 your output was this and then you could look at the circuit you could draw the truth table kind of off the top of your head and see what was happening now a flip-flop only has two inputs however one of them is this clock and the clock is a little bit different I'll show you why so let's say you have I'm going to draw what I'm going to right now is let me draw some waveforms truth tables don't really work when it comes to flip-flops and the reason for that is that flip-flops are triggered on ages the edge of a clock so a drill clock up here before I'll read rod 95 might maybe 99% of the time the positive edge is what you are going to care about as an FPGA designer or the rising edge that means when the clock goes from a zero to a one where does that happen happens here here and here and if I drill the one okay so in this particular waveform here you can see three outs are four rising edges rising edges let's focus on rising edges rising edges tell your flip-flop look at what your data is doing and make your output do that thing rising edges are what tell your flip-flop to move to do another cycle to do a turn it's a little if you imagine your flip up as a gear they say chunk you know they chunk your gear forward one cycle so let's I'm going to draw a waveform down so here's your data data or your D input let's say it does something like this and this is this is time so time this is this is a old previous time this is kind of now time so this is what happens over a period of who knows a nanosecond a millisecond a second who knows some amount of time and here is your clock and your clock does something looks like so the question is given this waveform for your data D input and your clock input what does your output look like again if it was a truth table you just look at it but flip-flops require you to look at things in time so this is again time I'm going to do a positive edge triggered flip-flop or a rising edge triggered flip-flop and rising edge of the clock so what you need to think to yourself is what does the output cube do on the rising edges D a D flip-flop will the output will follow the input but only on the rising edges so what that means is the output will start low and then the rising edge of the clock comes along right here rising edge from 0 to 1 so the flip top will say okay I see a rising edge of my clock what does the data look like at that rising edge so you were to draw some dotted line here and say at this particular moment in time sent let's sample the data let's take a look at it sample it and latch register that this is why they're called registers because it looks like the data at that time and it registers it to the output so a flip-flop and register it's another word for the same component inside of an FPGA so rising edge comes along I'm going to register that input to this output and then I'm going to stay low and I'm going to stay low until I see not a falling edge here but another rising edge which occurs right here so I can guarantee that for this amount of time Q is going to be low again it's low still even though D has gone high at this time here's the moment in time where D goes high Q doesn't know about it it doesn't see it it only can see that happen on the rising edge which doesn't occur until out here so Q is continues to be low continues to be a zero until this rising edge comes along here and it says it samples D again and it samples a one so Q will then become a one so there you go this is what your output looks like if you were to look at it over time you'll notice it looks like your input but it's shifted in time a little bit and it's aligned to your clock edges so your output of your flip-flops will always be aligned to the rising edge of your clock again it's an abstract concept when you first think about it but we'll do another example here and further down the line it's going to become more obvious as to how this works this is very fundamental to understand so let's do another example let's see let's do something clock is like this data does well what does Q do we will think about it take a guess I like to think about a little bit Q is going to start low sees a rising edge here and it sees a rising edge here and those are the only points where it's going to sample your data so it's going to say what is the data at this point it's a zero so I'm going to be zero and I don't even care that the data goes high right there q the output doesn't see it so it stays zero and then it's you seen another output another rising edge here what is my D input doing it's still low so I'm just going to stay well so Q never sees the fact that there is a pulse on your data line because it doesn't align with any clock edge so Q never goes high it saves the whole time now what happens if we do like this okay rising into the clock is where we care about what happens to queue there are your rising edges so here the possibility possible spots where queue can change it's going to start low it's gonna get to a rising edge it's going to sample D there we go it's going to stay high even though he goes low here Q doesn't see it here is a rising edge here Q goes back low again here's another rising edge q goes back high again and then it stays out like that so there you go so hopefully this would feel a little bit more clear as to what happens with a D flip-flop now that's just one flip-flop what happens if you have two two flip-flops I'll draw the circuit out for what what that might look like first here's your clock here's D here's Q is your clock here's D here's Q here's your input let's call this I'm going to wire the output of flip-flop one to the input of flip-flop - and now my output here is out we're going to call this let's see let's call this q1 call this Q - and this could be as d1 and d2 can be the same d2 in q1 of the same thing and here's your clock so so this is kind of something interesting clock both of your flip-flops share a clock input that's kind of interesting so they share a clock input then that means that they are tied together so I'm going to draw the waveform what happens here with two flip-flops cascaded back-to-back let's see I shot up here maybe so we have give us some room and d1 we're going to have it's called q1 we're going to have q2 and we're going to have our clock so I'm going to I'm just going to draw an example waveform of what would happen here and again it's gonna be a little abstract to think about it first but it becomes more natural so let's let's just get let's get started so three possible rising edges here here here so let's say our data starts low and it goes high here and then it stays high for the rest of the time what happens to q1 and q2 I will show you q1 and q2 are both always looking at the data line or at their at their particular input line so q1 is looking at d1 and it is low and it gets to this we can do q1 independently of q2 because the q1 only depends on d1 and your clock so let's do the whole q1 first so q1 says okay here's a rising edge I'm going to sample my data I'm going to be low and I'm going to stay low until the next rising edge here is your next rising edge so stuff drawn these so now another rising edge comes along q1 says what's my data and it's a 1 I'm going to go high and here's another rising edge here samples the data again stays high q1 stays high but it is a little bit goes high a little bit later than your data 1 goes high good now what does Q 2 do the second flip-flop in the cascaded chain q2 looks at Q 1 Q 1 and D 2 are the same so we'll drop out there we wired the output of q1 to the input of q2 so q2 is looking at Q 1 / T 2 whatever you want Cup so Q 2 looks at the input here so here's you this is the inputs of the second flip-flop and it says okay the input is low so I'm going to stay allow and then it looks at the input again what do you think is going to happen here kind of hard to tell isn't it is that edge a 0 or is that a 1 when you look at these signals you actually see these signals when you are building your FPGA if you use a simulation tool they these are called waveforms these actually you will see these waveforms appear and this happens all the time and you need to think about what this actually means if I am sampling this edge this data right here with this flip-flop here what does Q to do and I will tell you it's not intuitive but it doesn't see this happen when it's what it actually sees is it sees this as a zero it does not see it as a 1 okay take it for granted for now I will explain why but it sees this said okay I see this this one high but I see a zero on the line so I'm going to stay well it samples it again now D 2 Q 1 is high it's not it's not transitioning like it was here so here is where Q 2 goes high this is very important and a little bit confusing Q 2 is delayed by one clock cycle from Q 1 and repeat then Q 2 is delayed by one clock cycle from Q 1 so whatever happens on the output of Q 1 will happen to the output of q2 one clock cycle later which is exactly what you see right here on let's call this clock cycle one clock cycle two clock cycle three on clock cycle to q1 went high on clock cycle three q2 and high so it is delayed by one clock cycle now I'll say this if you don't understand this it's okay but the reason why it's delayed by one clock cycle is because it actually takes a little bit of time for this to occur so in the simulation world on the way on the whiteboard here I'm drawing this as it instantly goes high on this clock edge qq1 instantly goes high but in reality there is a little bit of time that it takes for this edge to go up on a physical circuit and that is actually due to propagation delay not important right now but I will talk about propagation delay in a future video for now just realize that when you see an edge like this on a waveform you are sampling the current value you're not sampling and you're not simply the next value you're sampling the current value which is what it was before that transition okay there you go so again if you're confused right now it's okay maybe rewatch the video think about a little bit more I'm going to show more examples in the future of waveforms and clock edges and things like that it's a bit of an abstract concept but it is critically important the reason why it's critically important is that flip-flops keep state inside of an FPGA they are the things that you use to know what happened previously so you have an input and it changes what was the input before it changed that is done with flip-flops so they are critically important to an FPGA designer it's a little it's an abstract concept take some time to get used to but flip-flops and look-up tables are the two most important parts of an FPGA we're going to get into exactly how these are created with your VHDL or Verilog code in future videos but this is the introduction to how I work so I look forward to continuing our fpga development in the future thanks for watching this tutorial for NAND landcom I am hustle

Channel: nandland

Views: 123,354

Keywords: FPGA, Flip-Flop, Register, Field Programmable Gate Array

Id: lrXjuotxqzE

Length: 24min 13sec (1453 seconds)

Published: Mon Mar 02 2015