Example Interview Questions for a job in FPGA, VHDL, Verilog

[Music] this is the second video in a series where I'm talking about how to get a job working with FPGA VHDL and Verilog the previous video was how to write a great resume to get you in the door to get you this interview so now you're in the interview congratulations you are at a great resume check out the previous video if you want to get some tips on how to write a great resume to get you in the door but let's assume that you you're in that you've been brought in and you want to be put you're gonna be poked and prodded by the interviewer I'm just gonna be me I'm gonna interview you I'm gonna give you some example interview questions in this video and try to get you kind of thinking about some common questions that you might hear in an interview for a digital designer working with FPGAs so I have some example questions I'm gonna run through them what I'm gonna do is ask the questions and probably give five seconds pause and what the purpose of this video is that you can practice so pretend like you're interviewing with me for your job you can pause the video give your answer to me I'm not gonna be here and obviously we're not there yet with the internet but maybe someday and then just practice answering some technical questions take treat this like a serious thing and maybe it'll help you I'll give you some ability to rehearse here we go welcome to the job interview so happy to have you here this is gonna be a technical interview and I'm just gonna jump right in now can you tell me what are a few types of flip-flops by the way should have said this at the end of the video I'm gonna go back through all these questions and give you the answers so if you have any questions or if you're unsure stay tuned great next question name a few types of latches please can you describe the difference between a flip-flop and a latch for me now why might you choose to use an FPGA in your design in the first place what does a for-loop do in synthesizable code and does it work the same way as in a software language like C maybe explain the differences there you describe a few differences between SRAM and DRAM for me what is the purpose of a PLL describe the difference between inference and instantiation in an FPGA design tell me what is metastability and maybe something you do to prevent it what is a FIFO what is a block ram inside of an FPGA describe to me how a UART works and maybe where it might be used what is the difference between synchronous and asynchronous logic what is a shift register in an FPGA describe some high-level differences between VHDL and Verilog tell me some things you should be concerned about when you're crossing clock domains inside of an FPGA describe to me setup and hold time and what happens if they're violated talk about some of the differences between a mealy machine and a Moore machine talking about state machines what is the purpose of synthesis tools what happens during place and route if you tell me what is a Surtees transceiver and where might they be used what is the purpose of a DSP tile inside of an FPGA those are the technical questions that I have I'd also like to know you tell me about some projects that you've done or some technologies that you've worked with and here I just want you to just tell me talk about what's interesting to you and what you've worked on all right so what do you think how confident did you feel answering some of those questions if you were able to answer all those questions I think you'd actually do really well on a job interview if you are a little unsure of some of the answers well stay tuned because I'm about to talk through them all this might take a while to talk through all these questions I'm not gonna go into a ton of detail so if you have more further reading if any of them if you've never heard of one of you know the answer is one of these questions before if you never heard of a DSP tile for example you might want to do some extra research about about that but I'll just talk through quickly some of the answer that I think would be good to give that would give me at least some confidence that you had some idea what you were talking about all right number one name a few types of flip-flops JK flip-flop D flip-flop T flip-flop if you don't know what a flip-flop lays that's gonna be a big problem for you that's like the simplest question so figure out what a flip-flop is name a few types of latches SR JK latch and latches a pretty fundamental concept so read about that describe the difference between a flip-flop and a latch main difference is that a flip-flop uses a clock a latch does not use a clock in general I never recommend using latches inside of an FPGA design unless you have a really good reason to do so and most likely you don't so don't use latches why might you choose to use an FPGA in your design well there's a lot of reasons maybe you have a lot of i/o requirements and you need some really huge FPGA with a thousand pins which exist and they're massive maybe you have some really high memory bandwidth requirements where you got to send and receive a lot of data through a DDR interface let's see maybe you have to do tons of math operations very quickly so a lot of multiply and accumulations maybe you do some some filters high speed data processing image processing things like that those are all great applications for FPGAs what is a for loop do and synthesizable code a for loop in VHDL and Verilog do not behave the same way as they do in C in VHDL and Verilog in synthesizable VHDL and Verilog a for loop is used to replicate or duplicate instructions it is not used to step through something one clock cycle at a time it expands all of the logic that's inside the for loop and executes it all on the same clock cycle and if you are unfamiliar with that just do some research I created a page about it in the inland describe the differences between SRAM and DRAM SRAM is static random-access memory DRAM is dynamic random-access memory they're both used for storage of data off chip so off your FPGA there are external devices they the big difference is that DRAM is much faster and larger and if DRAM is more meant for large data transfers externally so that better all sequential data transfers SRAM is usually non sequential kind of random transfers to an external part of memory not a lot of them maybe you want to write 16 bits only externally at address 10 and then at address a thousand you want to write another different 16 bits I had a 500 you want to write a different 16 bits and you're jumping all around through memory that's a much better application for SRAM versus DRAM is like I want to store an entire image from this camera off chip that's a great application for DRAM hmm okay what is the purpose of a PLL PLL stands for phase lock loop and it's commonly used inside the FPGA to generate other clocks so you have a clock coming into your pol pol spins it up to some high frequency and then you can use dividers off of that high frequency to generate other clock frequencies used inside your FPGA describe the differences between inference and instantiation when you infer some block that means that you're writing VHDL or Verilog to describe to the tools the synthesis tools that you you want a block ram for example so you might create a piece of memory like reg mem 7 down to 0 and you make it 256 deep the tools might infer a block Ram meaning they think that what you want is a block Ram they might infer it incorrectly and just infer a whole bunch of flip-flops and give you some memory that you didn't actually want instantiation is take literally instantiating a block ramp component which every vendor is a little bit different with how instantiation works for their primitives so if you want to instantiate a Xilinx block Ram versus an altaira or Intel I guess now block Ram they're a little bit different with their templates so inference one benefit to inference is that it's portable between vendors so if you infer a blocker I'm over here and it works and you infer blocker over here lattice and you know lattice and Xilinx or whatever then you can port your code a little bit more easily between venters much probably create a page about that cuz that's kind of an interesting concept okay what is minused ability how would you prevent it meda stability is some unpredictable or unknown state of a signal inside of your fpga so happens a lot on bringing some signal anything external bringing inside your FPGA or crossing clock domains this is the two situations where metastability can happen and in general if you just said the word like oh you double flop it to remove metastability that would be a good enough answer for me to to know that you understood at least some basics about metastability i wouldn't ask you to write an essay about it or anything what is a FIFO FIFO FIFO is a memory storage element if I so stands for first-in first-out meaning the first piece today that comes into it is the first thing that goes out of it they're commonly used in FPGAs they're usually made out of registers or block Rams they're common for storing up data temporarily or for crossing clock domains things like that that would be a good enough answer for me to have confidence that you have worked with a FIFO one other tip you know maybe while we're just talking about this is like if you don't know an answer but you've heard of something before like let's say you've heard of Python you know means first-in first-out that you've never used it before an FPGA design yeah I'd love to I love to see people trying to figure things out in an interview you know even if you don't know for sure how to instantiate a FIFO or why it might be used you know pulling on some threads in your brain you're like oh four it means first-in first-out so that must mean that the first piece of data that goes into it is also the first one that goes out of it so maybe it's like a buffer of some sort thing yeah working through some of those things you know being upfront with the interview and saying well I'm not sure however and kind of going off from there that's always great like I'm much rather you do that than just sit there and say I'm not sure because I don't want to be wrong being wrong is most of being an engineer what is a block Ram block Ram is a storage element inside of an FPGA it's usually something like sixteen kilobits 32 kilobits it can be dynamically sized to have different widths and depths and store some data one bit wide 16k deep or two bits wide 8k deep commonly turned into typos dual port memories things like that I have a whole page on what is a background check it out describe a UART and where it might be used you aren't stands for Universal asynchronous receiver transmitter it's a super common and very simple way to get data in and out of an FPGA it's low pin count low bandwidth interface if you want to go between like a microcontroller or an FPGA you are it's a pretty good candidate for that I'm gonna link to this text version of this page as well just kind of what I'm cheating off of here to give you some more details and there's further reading on that page too so check out the description below what is the difference between synchronous and asynchronous logic synchronous is clocked asynchronous is no clock that would be a good enough answer for that question most logic inside of an FPGA is synchronous logic meaning it's registers that's the bulk of your of your what the FPGA is made out of and it's super common to use in most communication interfaces are synchronous base there's a clock involved SPI i2c USB those all have clocks versus USB recovery stuff anyway you are today synchronous but the majority are synchronous what is a shift register inside of an FPGA shift register is useful for creating some small delays useful for doing something some time waiting for some number of clock cycles so you have some data coming in and it shifts down this this shift register chain and 10 clock cycles later it comes out so it's useful for converting serial data to parallel data or parallel to serial things like that describes in differences between VHDL and Verilog you could just tell me which one you like better which one you have more experience with in general VHDL is much more strongly typed been bare log so you'll get a lot more syntax checking in the compile stage versus very log we'll just let a lot of things fly if you want to assign an integer to a three bit register and véra log it sounds great no problem not going to flag a warning if you do that in VHDL it'll cut your head off so strongly typed languages versus not strongly typed bare log looks a lot more like C than VHDL this what should you be concerned about when crossing clock domains in an FPGA creating a metastability condition is really what is the problem if you're going from a slow domain to a fast domain or fast to slow usually to be careful and make sure that you don't lose any data along the way or corrupt the data so often double flopping go changing clapping means is helpful or using some sort of buffer storage element like a FIFO for example is great and you can talk for a long time about that so I have actually a link to how to cross clock domain successfully inside of an FPGA if you want to read more about that describes setup and hold time and what happens if they're violated set-up time is the amount of time that the signal needs to be stable going into a flip-flop before the rising edge of the clock comes along to register it to the output so if you and then hold time is the amount of time that that signal on the input needs to be unchanging after the clock edge so it's before the clock edge setup after the clock edge hold if those setup and hold times are not violated you're good if they are violated you potentially create a metastable condition inside your FPGA where you can't guarantee the output of the flip-flop meaning like worst case temperature worst case voltage worst case blah blah blah you might have an you might have a timing error you might create a master bill metastable condition timing errors are bad and you should never have them so that's make sure you don't when you go through your place and wrap tools which I think we have a question about that what is the difference between a mealy and a Moore machine they're both state machines that are used to control flow through an FPGA design mealy machines depend on the current state as well as an input to know where to go next a Moore machine just depends on the current state in order to know which date to go to next personally I like more machines a little bit better I find them a little simpler and so I generally use those what is the purpose of synthesis tools synthesis tools are is the tools usually provided by the FPGA vendor and the purpose is to translate your VHDL or your very log code into discrete gates that the FPGA has inside of it so flip-flops look up tables multiplies things like that block Rams translates your design what happens during place and route placement route takes the after the synthesis process happens place and route is where it takes those individual gates and look up tables and actually assigns them to a very specific you go here and you go here and routes them with wires on the actual FPGA and the main thing that places route is trying to do is trying to do a tiny enclosure meaning it's trying to given the clock rate that your FPGA design is running at trying to make sure that all of the all of the start and end points for signals is going to happen in one clock cycle if it doesn't happen in one clock cycle you're gonna violate set-up time you're gonna violate hold time the propagation delay is gonna be too long and you're gonna have a timing error and again timing errors are bad so don't do that surtees what does a Surtees transceiver and how are they used sir DS stands for serializer deserialize err it's high speed way of sending data across low pin count interface it's commonly used for PCI Express SATA Gigabit Ethernet high-speed video applications things like that that'd be a good enough answer for me to be happy if you want to talk more about series I like series talking about for a while what is the purpose of a DSP tile an FPGA if you just said it does multiplies better that's pretty good good enough it DSPs do fast multiply accumulated operations so if you have a large filter design for example and you have a lot of taps off that filter in each tap as a multiply you can push each one of those to adea's b48 tile in silence for example and it will you'll be able to increase the clock rate of your filter if you don't have DSP tiles you can still do multiply operations inside of an FPGA but you just won't be able to run it very quickly you might have to take extra clock cycles to get an output to get an answer that's pretty much it you know talk about your own experience using FPGA s talk about projects talk about what you like what you don't like things like that I recommend putting a github repository 2 on your resume to show some source code so if people want to see some examples of what you've done you'll have that there for them I hope this has been helpful video if it has been helpful for you to practice some of your skills please consider becoming a donor on my patreon page which I will link to in the description below and if you want to practice working with FPGAs check out the go board go to namland com buy yourself a go board those one of those two or both would be great ways to support me and keep me making great content thanks

Channel: nandland

Views: 69,011

Keywords: fpga, job, interview, example, questions, practice, tutorial, career, resume

Id: 9U9R4IxIACs

Length: 20min 34sec (1234 seconds)

Published: Sun Jan 20 2019