There's Plenty Moore Room: IBM's New 2nm CPU

cast your minds forward to what you think 2024 is gonna be 128 cores 256 cores will we finally hit 10 gigahertz ddr6 cxl who knows what i can tell you is that ibm has already got its two nanometer chip in production what's your minimum specification so before we start talking about ibm's two nanometer chip i want to speak about the whole nanometer ordeal uh as you may or may not know uh process nodes are typically given the name of nanometers so we had 19 nanometer 60 nanometer 45 nanometer 28 nanometer 14 10 7 5 and the list goes on and we've seen robots all the way down to 1.4 nanometer now back in the early days of semiconductor design transistors were planar they were flat on the silicon and the number referred to essentially how close you could pack those transistors it was to do with the minimum wire distancing at the time so as process nodes got smaller we were able to pack those uh transistors together denser and do more per unit area now when intel moved to 22 nanometer it introduced its first generation finfet technology no longer were the transistors planar we actually built them out of the silicon in a 3d format as transistors get ever smaller one way to achieve this is to get tighter control by having the gate wrap around the channel as much as possible this is intel's new 3d transistor with the 3d transistors architecture we replace the flat two-dimensional stream with one or more three-dimensional fins the control is on all three sides of each fin rather than just one as in the planar transistor we call this a trigate transistor and its real advantage over planar is the ability to operate at lower voltage with lower leakage providing an unprecedented combination of improved performance and energy efficiency and then 40 nanometer had its second generation we then saw tsmc and samsung come in with finfets for their 1614 enemies processes from that point on the naming got a bit skew-if so it went down from 14 to 10 to seven even though the actual dimensions of the transistor haven't gone down from 14 to 10 to seven the idea is that the name kind of reflects the effective planar transistor and not the actual transistor involved this is why why we're in a situation where you know one company seven nanometer is about equivalent to another company's 10 nanometer there are different parts of the transistor that you could call 10 nanometer or 40 nanometer or seven nanometer actually um intel's 14 nanometer if you look at some of the line thicknesses um some of the protective barriers are as small as eight nanometers so why aren't we calling that eight nanometer for example because that's the smallest feature that we can measure through scanning electron microscopy the point is it's all got a bit skew-if and one way to do that is through transistor density so this is talking about how many millions of transistors can you fit in a tiny square millimeter this gives us more of a benchmark of kind of where we are in terms of process node scaling so current intel 10 nanometer tsmc7 nanometer and then i thought i'd just make a little bit of news this morning and tell you um that um as we talked about before we said we would be shipping our first 10 nanometer codename canon lake parts just before the end of the year we're actually we actually did that so we started shipping our first 10 nanometer codename canon lake cars just before the end of the year and we're on schedule to be ramping throughout 2018 as we said previously they're around this of 100 million transistors per square millimeter mark and uh future nodes from both companies they're saying you know 1.7x density increase 1.5x density increase and this is kind of where we get to ibm on two nanometer now i know what you're thinking ian ibm doesn't manufacture chips why are they saying they have two nanometer well ibm is a research facility you may have seen recently that intel announced it was going to do a collaboration with ibm it's in my video talking about intel's idm 2.0 which you can find in the link here what they do as a research partner for samsung and alpha intel is essentially develop license and patent technologies that can be used in a manufacturing process ibm is a world leader in uh patents being issued for process technologies and all sorts of other payments as well i think they're they're on a march of you know several thousand payments a year maybe even five figures by now but the point is that's a big part of the company as a whole is simply just research so they did research into seven nanometer into five nanometer into three nanometer before everybody else even thought about implementing it in an actual product and today ibm is announcing that they've created their first two nanometer chip now how are they classifying it as two nanometer they didn't really say by what metrics they're classifying as two nanometer but they did gather give us some density numbers they said 50 billion transistors in an area the size of your thumbnail i asked exactly what size thumbnail is because thumbnails can be big small uh you know small as 50 square millimeters largest 250 square millimeters if you're a giant they came back and said 150 square millimeters which puts the uh the transistor density at about 333 million transistors per square millimeter and if we look at the table of what current process nodes do we'll see that that's a sizeable jump here's my table from my article at anantek so with ibm two nanometer at 333 million uh transistors per square milliliter tsmc's three nanometer is meant to be around 292. uh it's current five nanometers 171. seven nanometer 91. intel is saying 237 for its seven nanometer process and then numbers for samsung roughly mirror that from tsmc now it should be noted that this is peak transistor density so this is current currently used for the non-frequency critical parts of the chip when you have a chip that has logic which requires high frequency you don't use the most dense transistor libraries because they have two higher thermal density typically they're about half as dense as the peak quoted trans transistor density also different fabs actually have different counting methodologies for their transistor density depending on how many flip flops and other sort of transistor type structures are actually on the die so these numbers are roughly in the same area we've seen some predictions from ic knowledge i think which are actually about 10 higher than the official quoted values but this is at least a good ballpark uh to consider where this is coming from so this two nanometer chip two two nanometer wafer they created a 300 millimeter 12 inch wafer uh with two nanometer chips the chip is essentially a vehicle for lots of different transistor designs so they can check to see how they all work uh you've got you know different variations in say power rails in sram size they wouldn't tell us our their sram cell size unfortunately um they said they've got multiple vt devices plus minus 200 millivolts i'll link down to a couple of papers they're the first with bottom dielectric isolation and if we actually look at a picture of the transistors that they provided to us it shows that the two nanometer from ibm is using uh nanosheets technology or gate all around transistors we call them garfetts gaa garfetts and ibm's three nanometer designs also had these gate all around designs and compared to the current foundries on the market we suspect intel is going to be uh using uh nano sheets at five nanometer samsung is going to be using them at three nanometer and it looks like tsmc is going to be using them at two nanometer so there's a bit of variation in the industry um intel seems to be you know kind of on the whole nanometer naming at least um as early as possible same with 22 nanometer they were first to finfets back in the day nanosheets are the way forward they're a lot better than finfets in the sense that you can tailor your transistors to the right voltage and response you need whereas current transistor current finfets designs you're having to deal with discrete numbers of transistors with nanosheets you can vary the size and get a more continuous response rather than individual discrete responses for anybody who follows transistor design this chip was fabbed in their albany plant in new york this is where ibm does a lot of their research i actually now have an open invitation to go visit the fab that they have there the research fair but albany when we get traveling again i definitely want to go do that because just north of there is malta for global foundries and they're fab 8 leading edge process node i've still got an open invite to go there and then you know just slightly southeast of that is wilton connecticut that's where asml build euv machines so i'd also like to go visit there in terms of performance of these two nanometer chips ibm is claiming a 45 performance increase at the same power as seven nanometer or a seventy five percent power decrease at the same performance against seven nanometer i asked exactly how they're going about calculating these numbers and they just say industry standards they won't go any deeper than that unfortunately though i really would like to you know have a look to see exactly how they're calculating that in speaking with one of the chief engineers over at ibm he said in terms of this technology actually coming to market well it depends on partner licensing and patent and you know deployment it's still very much a 300 millimeter wafer technology right now he says that they'll be working with partners soon and look to a potential deployment in late 2024 in terms of actual product and high volume manufacturing you might think around 2025 so this is a kind of time scale for these things um if you're ever wondering how far out companies do their manufacturing design four or five years is actually a good number for that sort of path finding not the immediate next node maybe not the node after but definitely the node after that is in that sort of five to seven year time frame and companies like ibm are doing a lot of the research on that front they obviously have a lot of collaboration in academia especially and some you know some private collaborations as well and if you ever want to find out you know what kind of is the stuff on the leading edge of this conferences like iedm isscc they're really good for research papers into the next generation of technology design i mean we're still dealing with silicon transistors here we still haven't covered you know three five transistors 2d transistors and what could be coming after silicon for this uh transistor for these two two nanometer transistors actually uh they did say that they're now using euv on pretty much every part of the process so front end of line middle end of line and back end of line what this means is more euv means that the features are more well defined which means that they can increase the transistor density as well they did say that it's still single patterning euv now if you follow uh finfet and uh duv process no technology you'll know that we're in your double patterning and quad patterning and all those sorts of technologies have helped elongate pre-euv technologies we still have that to go and for euv two nanometer we're still on single patterning so imagine what quad patterning on euv might bring so if you go look at so on the right that's around the left that's how we used to print an x right on a chip so the optical wave length let us resolve it's 130 nanometer we can resolve a little lower than that you print an x but as you know we kept printing this finer and finer and it turns out when you start printing finer that the light literally interferes with itself which is kind of a drag but it turns out that's a transverse function you can calculate so the mask actually prints something different so it interferes with itself you get an x on the chip and that was be honest was getting wiggler and wiggler and on the right what was happening just not too long ago in 2014. the thing you had to print to get an x was getting more complicated because the thing you're printing was much smaller in a way like the light there's you know a million physicists working on this so and here's kind of what happened so the world believes we shrunk transistors by having the wavelength of light get smaller and at some point it kind of tapped out and then between 2007 or 8 there in 2018 or 19 right they were using all kinds of tricks to get the devices to keep shrinking right and then we invented the uv and started bringing on that that online and if you do the math we were just discussing it this morning the 193 nanometer let us actually resolve to 80 nanometers without much trick the 13.5 resolves to eight eighty squared over eight squared is a hundred x so does everybody know that was that big news in the newspapers that ev machines is enabling a hundred x shrink of transistors that was the fine print under moore's law's dead right so the so here we are in 2020 printing x is like they were meant to be printed they're just hexes now there's a lot of room to go shrink the light and then there's room to do all the tricks because optics works and interference is the thing and you know we'll do all those things but at a whole bunch of other dimensions of this we'll do it so what's my minimum specification here i have asked ibm if i can take a bite of the wafer they haven't answered i would have to go visit to find out if you stay tuned there'll be a cat tax at the end but i need to give a big thanks to all the patrons who make this video possible if you feel like denoting then patreon.com take potato it really does help out and i really love all of you who do if you like this video please give it a thumbs up if you didn't yo leave a comment down below and let me know what you think either way two nanometer what do you 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Channel: TechTechPotato

Views: 482,328

Keywords: 7nm, 5nm, 3nm, 2nm, IBM 2nm, 1.4nm, future chip, future 2nm, Albany, nanosheet, gate all around, transistors, 2nm transistors, what is a nanometer, what is a transistor, 2 nanometer, ibm, does ibm make chips, 2nm cpu, 2nm gpu, 2nm fpga, future apple cpu, future intel cpu, intel 2nm, first 2nm, transistor density, best cpu, most advanced cpu, fastest cpu, most complex cpu, silicon, silicon wafer, 3d transistors, gaafet, ian, cutress, techtechpotato, jim keller

Id: DZ0yfEnwipo

Length: 15min 45sec (945 seconds)

Published: Thu May 06 2021