Intel Performance Leadership in 2025: Beyond Nanometers

i'm in a happy mood because they've finally done it intel is changing its node names what's your minimum specification lenode makes managing cloud infrastructure easy with same pricing a full-featured api and 100 human support whether it's a personal vpn game server website or a big-ass gpu solution new users controller node today with a free 100 60-day credit at lenovo.com so today as in right now when this video is going live intel is having its intel accelerated event in which ceo pat gelsinger and dr ang kaliha are presenting the future of intel's process node and packaging manufacturing now it's been a while since we've seen detailed updated road maps from intel and this event is exactly that it's a chance for the company to put one foot forward and say these are the process nodes this is what we're doing and when coupled with that there's a little bit of a surprise where intel is changing the name of its nodes so intel process node naming we already know about 22 nanometer 14 nanometer 14 plus 14 plus plus 14 plus plus plus plus tick tock tick tock tick tock tick tock 10 10 plus 10 plus plus which then became 10 plus then 10 super thin 10 nanometer enhanced superfin then 7 nanometer and then something about gate all around being on five nanometer sometime soon whatever way you want to remember intel's process node naming it's a mess it is simply a mess not only is it a mess but every time i explain it every time anybody in the press explains it any time intel explains it when comparing to their other foundries samsung and tsmc they have to explain that hey look our 10 nanometer roughly the same density as tsmc's seven nanometer intel seven nanometer roughly the same transistor density as tsmc's five nanometer given that these numbers are just names and don't actually mean anything physical the fact that they become marketing terms with a numerical order has really given intel put or put intel essentially on the back foot and this is going to come to a head when intel is going to offer its foundry services over the next few years customers are going to have to decide between a tsmc an intel a samsung maybe even a global foundries process and they're going to have these numerical values and they're going to have to decide which one they want for the price performance now intel has decided based on feedback from people like me from other press from other analysts from customers that is going to change its node name to be in more in line with the rest of the industry now let's put it into perspective here normally when we're talking about node changes we either talk about a full node or a half node now these are relatively new names in of themselves but the idea is that if you have a major manufacturing change that's called a full node jump now if you have a minor change or an update that's called a half node jump or maybe multiple small updates equal a half node now intel's way of describing those very small updates was to put a plus plus plus plus plus plus samsung and tsmc on the other hand kept decreasing the number so in samsung's case you have 10 nanometer eight nanometer seven lpp six lpp five lpe even four lp are all roughly based on the same process node arrangement so while samsung and tsmc were going down in number intel kept its numbers the same and as a result were in this situation where intel 10 became roughly you know the same as intel 7. what intel is doing today is realigning their node naming so intel 10 10 super thin that stays the same that's already out in the market that's already productized that's going to stay the same next is what we used to call 10 nanometer enhanced superfin this is what old lake is going to be on this is what sapphire rapids is going to be on that is now intel 7 or until 7 nanometer the documents we've been getting says intel 7 but it's going to be weird not saying nanometer so intel seven nanometer that's going to come with the benefits of superfin now after intel seven or what used to or ten enhanced suffin is intel four intel are gonna skip the number five for some reason but what used to be intel seven is now intel four what used to be intel seven nanometer in the old scheme is now intel four this is where intel is going to introduce euv on a substantial number of layers in the design and we're going to get enhanced power performance uplifts and all that good stuff that comes with a major node change after intel 4 becomes intel 3 which used to be called 7 plus and that is going to be a more it's kind of that's where intel kind of changes its design scheme to be a bit more modular so intel 3 will be roughly the same as intel 4 but with just higher performance high density libraries and obviously next generation finfet transistors now after three nanometer usually we expect two nanometer but intel is changing up and here's your answer is what we're going to happen when we're going to run out of nanometer numbers we're going to move to angstroms now nanometer is uh 10 to the negative 9 and strong is 10 to the negative 10 so 10 am angstroms equals one nanometer however because these are all names it doesn't actually measure anything physical so to go back intel 3 then becomes intel 20 a and this is actually going to be one of intel's big important notes intel is saying this is coming out in 2024 and it's going to be the first to use intel's new ribbon fet transistors so if you've been following transistor technology we've been dealing with benefit transistors for how many years now since you know intel's 22 nanometer and we've had your first gen second gen 3rd gen 4th gen but at some point finfet transistors are running out of steam you can only go 3d up so much beyond that as we're spoken about in this channel you have gate all around transistors where you essentially have sheets nano sheets nano ribbons stacked up on top of each other and that's where you get your scaling from intel is going to introduce its first generation gate all around design which they're marketing as ribbon fets with intel 20a coming 2024. also in intel 20a is going to become what intel is calling power vias which is backside power delivery now if you think about a chip layers of transistors and then on top of the transistors you build all the wires that you connect the transistors together and that's how you move data around and inside there you've also got a bit of power and you've got to manage the power and how it interacts with the other wires so you don't get interference and lose your signal with power vias or backside power delivery instead of having that sort of cake arrangement of layers and layers and layers you now have a sandwich your filling in the middle is transistors on one side of that you have the communication wires and on the other side of that you have the power connectors so now instead of becoming a cake you have a sandwich and intel 20a will be the first process node to offer this technology uh intel is saying that four until three intel 20a and beyond will all be offered to foundry customers so this is where kind of intel shifts away from finfets finfets have been in the industry for a long time they've made intel a lot of money so let's see how intel can uh execute essentially with these ribbon fets and power vias now intel also explains that after 20a will be 18 a essentially 18 angstroms but again it's not a measurement it's just a name this is where intel will be using a second generation euv so euv extreme ultraviolet lithography uh this is what has been essentially bringing forward the next generation of computer designs getting those transistors really really small inside the machine there's a massive lens the last stage and that has what's called a numerical aperture the current value of that numerical aperture is 0.33 the new version will be .55 also known as high numerical aperture or high n a in short this just allows you to have a better contrast better resolution with your manufacturing and intel is going to be the key customer for asml the company that makes these machines over tsmc and over samsung intel told us that they will be the first company to receive a high n a machine for volume production this is coming in 2025 and it also coincides with intel claiming that they will become leaders in performance in manufacturing performance leadership performance with their transistors in 2025. that all coincides right there with intel 18a process node and high in a design high in a euv now on top of all this on top of all process node we also have packaging now i've explained on this channel emib and foveros embedded multi-die interconnect bridge and fovros die to die stacking essentially 2.5 d and 3d intel has said that they have a roadmap for both technologies we'll have second generation emib uh coming uh after sapphire rapids which would be granite rapids 2023 2024 but the more important stuff is on the fauxvaros side so foveros dietary stacking we saw it in lakefield uh currently the little bumps in between the dyes uh they're spaced apart by 50 micron second gen foveros as used in meteor lake we'll be using uh 36 micron bump to pump is called the pitch that's the pitch dimension which offers a 2x increase in density beyond that we have third generation faux ross which they're calling foveros omni now if you follow this technology this is what we used to call odi omnidirectional interface but it's being renamed or marketed as foveros omni this brings the bump pitch down to 25 microns but when foveros was all about two dyes stacked on top of each other the whole point was that the top die has to be smaller than the bottom die to fit it on with odi the top die can be bigger so you essentially end up with an inverted hat where the brim is wider than the head bit so what this allows designs to do is instead of putting in those you know original first generation bumps you had to put data and power with the power causing you all the interference for signal integrity you move the power to the outside of the chip so you have massive pillars coming up from the substrate to the top die and then your bottom die can just deal with data and that actually makes it easier to make those faux ross bump die really really close down to 25 micron now beyond that intel also spoke about fourth generation photo riffs called fovaros direct if you've seen tsmc uh chip on wafer stacking uh or amd's vcash technology this is kind of what that is you're essentially getting two chips and just plunking them together similar sort of thing uh just copper copper bonding you have lots of things to get right when you design stuff like that but basically the bump pitch goes now down to 10 micron or a 6x increase in density for those uh data connections and there we have it that's intel accelerated in a nutshell i know the packaging stuff is you know a bit more esoteric than understanding what's going on with the process nodes i for one i'm really really glad intel's changed its process node naming i know a load of people will be annoyed confused saying isn't intel trying to change the game my argument is no you know what they've done for years is plus plus plus plus plus while their competitors have been reducing the numbers regardless of whether it's a full node or a half node transition or something in between what this does is it realigns intel to the rest of the industry rest of the industry we're doing one thing intel was doing another and intel decided you know with feedback from some of us saying we've got a good of design on our 10 10 nanometer csmc7 in terms of density so we're just going to align the numbers align the names and so now we have to talk about old lake being on seven nanometer sapphire rapids being on seven nanometer intel seven again not sure if nanometer is exactly part of the name and then we look at intel fourth euv intel three for more euv then intel 20a for new gate all around transistors fantastic i love this and i hope you guys do as well now you may think me saying that makes me an intel fanboy no i just love consistency and this just makes things more consistent the big question on all this is can intel execute we know intel has been having problems with its uh 10 nanometer portfolio for a number of years now intel the other day in their financial call ceo pat gilsinger said that intel is now making more wafers on 10 nanometer than they are in 14 nanometer which is a sizeable jump uh in what we expected those ratios to be though with uh next generation intel being on intel seven uh old lake and then intel four with euv really that's the intel four has got to be the sort of inflection point to see whether intel can actually progress forward in a more modular fashion with its process node designs and hopefully then it can execute on a much more regular cadence in line with its main competitor tsmc what's my minimum specification here well we're going to be holding intel to account we want intel to execute we want intel to be competitive because that's how this industry goes so we will be keeping close tabs on them to make sure that they absolutely do what they say they're doing [Music] so you

Channel: TechTechPotato

Views: 48,180

Keywords: intel, intel accelerated, intel process node, intel euv, intel high na, intel 10nm, intel 10sf, intel 10esf, intel 7, intel 4, intel 3, intel 20a, emib, foveros, foveros direct, foveros omni, transistor density, intel meteor lake, intel granite rapids, pat gelsinger, ian, cutress, techtechpotato, intel technology development, roadmap, intel roadmap, intel best cpu, intel best technology, tsmc, samsung, gaafet, intel ribbonfet, intel powervia

Id: 0PD7IJgbuWs

Length: 15min 29sec (929 seconds)

Published: Mon Jul 26 2021