Creating an AXI Peripheral in Vivado

hello and welcome to this video quick click video in this video you'll learn how to create an ACCI peripheral to which custom logic can be added to create a custom IP using the create and package IP feature of the guado this training assumes that you are familiar with designing IP subsystems in IV integrator you can watch some of the quick tech videos on IP inhibitor as shown on this slide in this quick take video we'll create a new project in Vivaro using the create and package IP feature we will then create a slave AXI peripheral we'll create a test bench and the necessary drivers for the peripheral for developing a software application in sdk will simulate the AXI peripheral in rubato to ensure that the registers of the AXI peripheral can be written and read from using an ACCI bus functional simulation model then we'll create a micro blaze processor based system in which we will add this custom IP the design will be then implemented and bitstream generated will then export the hardware to sdk and create a test application and generate an alpha finally we will launch our application on the target board KC 705 and verify its functionality we start our design by launching Vivaro and creating a new project from the Quick Start page we'll name the project and specify the location where the project will be saved we'll skip some of the other options for adding existing RTL IP constraints to the project at this time as everything needed for this project will be generated later we select boards in the default part page the Vado is board aware and it knows the physical connections present on our target board it can thus generate the appropriate physical and timing constraints for our target board based on the interfaces that we choose in our design we select the KC 705 target board here let's review the summary screen to make sure that all the options have been entered correctly and click finish once the project has been created we launch the create and package IP feature using this feature you can either package a new IP or you can create a custom XE peripheral to which your logic can then be added to make your own custom IP when you launch the create an IP package feature in a new project you have two choices you can package a pre-existing project directory or you can create an ACCI for peripheral we choose the creating a new activity for all and click Next in the next page we can specify several options such as name version display name description and the location where the IP will be created once type is created you can search for the IP in the IP catalog using the name given to this peripheral also note down the IP location this is where the IP repository is created on the add interfaces page you choose the number of interfaces that you want the AXI peripheral to have interfaces can be added by clicking the plus sign and delete it by selecting the Delete icon notice that the component symbol also gets updated as you add and delete interfaces several properties of the AXI for peripheral can be specified on this page you can specify the name of the AXI interface in the name field you can choose the type of ax afford per protocol desired the choices are lightful and stream you can specify whether the interface is created in a master mode or a slave mode you can also specify the data wait for the interface and the number of registers desired currently the number of registers supported by this feature for axle I turn phases between 4 to 512 for the purposes of this video we'll go with the default values click Next to get to them to creat peripheral summary page where you can either add the IP to the repository or edit the IP further to create a custom IP you can also create a test bench to verify the axe' for peripheral using an ACCI bus functional simulation model or you can test the IP in Hardware by using the JTAG 2 XE IP core in this case we will select the verify peripheral IP using AXI for BFM stimulation interface option and click on finish to create the XE peripheral [Music] as you notice a block design is created and AXI peripheral is instantiated and connected to the AXI bus functional model the design is then elaborated and simulation is launched the testbench that is created with this design exercises the bus functional model to generate several read and write transactions those transactions can then be verified in the simulation window as well as on the tickle console where the result of readwrite transactions are written now take a moment to look at the waveform window and also a tickle console to verify that write and read operations took place all right you will notice several statements in the tickle console showing the data written to the peripheral and the data read out from it if adding custom logic to this peripheral is desired you can add your custom logic to this peripheral at this time the peripheral can then be repackaged to turn it into a custom IP at this point we can close the simulation and exit project click OK to exit from Vlado next we'll create a new Lovato project to create a micro blaze based system in which we will instantiate the AXI peripheral that we just created again like before we'll create a Vivaro project using the default settings and making sure that we targeted to the KC 75 board take a moment to review the new project summary page to ensure that all the project settings have been entered correctly and click finish once the project created we need to create a block design we give a name to the block design and click OK you in the block design cameras we instantiate a microblaze processor notice that as the processor instantiated in the diagram canvas designers assistance becomes available to us click on the link to use the block automation in the run block automation dialog box will increase the depth of the memory to 32 kilobyte and let all the other remaining options to their default value once the basic subsystem is created we can instantiate the AXI for peripheral that we had created earlier to make the AXI prefer available in the IP catalog we need to add the repository containing this IP to the Vivaro project we do this by clicking on project settings under project manager and then selecting the IP icon in the left panel click on IP repository and then browse to the repository called IP repo and click select as soon as the IP repository is added to the project you can see the EXCI peripheral called my IP that was created earlier let's instantiate this IP now along with an UART light IP in the design the UART light is necessary to monitor communication between the hardware and software on our terminal window in SDK you will notice that designers assistance is available again which we can use to make quick connections of the newly instantiated IP to the microplane subsystem I mentioned earlier bravado is board aware and knows the interface is present on the KC 705 board as we use the designers assistance to make connection to the different interfaces on the board you will notice that the interfaces that are used in the design show up in the connected interfaces folder in the board pot interface window we only need to use the clock reset of the UART interfaces in this design use all of the items under connection automation link to complete the connectivity of the design with the design not complete let's make sure that the memory mapping for all the slaves in the design has been done correctly as the sleeps are instantiated in the design IP integrator assigns the memory to each of these automatically this memory mapping can be changed if desired in this case we'll leave the default memory map at this point we are ready to validate the design validating runs design rule checks on the design running DRC is successful and there are no design errors in this case we can tidy up the design and generate an optimum layout of the design by clicking on regenerate layout at this time we can save the block design with the block design now complete we generate output products and create a top-level wrapper file that is den sheets the block design in it now we need to implement the design which can be done by clicking on generate bitstream which will take the designs of synthesis implementation and finally generate bitstream generating that stream may take several minutes after bitstream has been generated open the implemented design once the implemented design is open ground a timing summary report to make sure that all constraints were mapped take a moment to look at any setup or whole-time violations in this case everything is good so we need to export the hardware so we can develop our software application to do this we'll export the hardware by selecting export hardware for SDK while exporting the design we selected the option to launch SDK so SDK launches in a new window in SDK will create an empty application project to which we can add some code to exercise the AXI for peripheral on the KC 705 target hardware let's create an empty application first by creating a new application project and specifying a name for the project in the templates page select empty application and click finish while creating the empty application SDK creates a self-test application for the AXI peril which we created in Vivaro earlier this self-test functions need to be called by our custom application code so essentially what we'll be doing here is just add a few lines of code in our application to call the function that performs the self-test of IP this self test routine called my IP self test basically writes four bytes of data and reads back those data bytes so we'll add a new file will call this file may not see in this file is where we will add a few lines of code to call the function that was created earlier for exercising our XE peripheral IP now we are ready to compile this code once compilation is done take a moment to look at the console for any warnings or errors that may have been flagged during the process in this case it appears that everything is good so we'll connect the monitor to monitor the communication between the hardware and the software with the monitor connected now we're ready to program the FPGA make sure that the bitstream selected is the correct bit stream for the project programming the FPGA may take a minute or so now that the FPGA has been programmed we can launch the elf file onto the hardware to do this we'll select the application code that we just created and launched it on hardware on the bottom right of the window you can see that the code is being launched on hardware and on the terminal you will see the results of the self-test that was performed the terminal window shows that for right transactions were performed followed by four read transactions and the data for the write and read matches so in this quick take video we have created new exe peripheral simulated using an ACCI bus functional model and then provide its functionality on the KC 705 board Ino microblaze based design we have seen how the create and package ID functionality in Novato allows you to create a master or a slave ax equal which can be used to create a custom IP thanks for watching the quick tech video

Channel: XilinxInc

Views: 34,327

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Keywords: axi peripheral, Package IP, IP Wizard, AXI Bus Functional Mode, custom IP, create IP, vivado package ip

Id: 8hzzVhPw6uw

Length: 17min 1sec (1021 seconds)

Published: Fri Apr 11 2014