Creating your first FPGA design in Vivado

welcome to the first lab video for engineering 3 2 1 3 digital systems and micro processes in this video we're going to get started with Vivaro and design a simple light switch for the Nexus 4 DDR Development Board whilst this is conceptually very simple this particular exercise is powerful because it provides us with a step-by-step guide on how to create a fully functioning FPGA design from nothing this includes describing the behavioral logic of a light switch in Verilog specifying connections to the Nexus 4 ddr's physical i/o using constraints and then synthesizing and implementing our design in Vivaro before loading it onto the FPGA the first thing that'll appear when you launch privado is this window and this allows us to create a project open an existing project or even open an example project we're going to go ahead and create our first project the first window that pops up simply informs us of the information required to complete or create a new project in this case we're going to name our project my first project and we're going to set the project location to be a directory somewhere well-known I'm not sure what the default is on your computer but I've created a folder under my documents called FPGA and I'm gonna store my project files in a subdirectory called projects make sure that this little tick box is ticked because then I'll make sure that all the the files that are created during your project stored within a subdirectory called my first project the next screen that comes up asks you to specify the project type so there are a few options here but the only one that we're gonna be dealing with is RTL project that stands for register transfer level project the only other one that might be interesting for you is example project because this provides you with a bunch of predefined templates created by Xilinx we don't have any sources to specify this time so you might as well make sure that this checkbox is ticked the next thing that Vivaro asks you to do is to specify a thing called a default part now what this is is the actual physical FPGA chip on whatever device you're targeting with your design so this is important because you know we're using the nexxus for DDR development board and that has a particular FPGA owner but if for example we're using a basis three then it uses a different FPGA chip and the reason this is important is because the different FPGA is will have a different number of pins and they'll also have different pin assignments to the various i/o on the development board so in our case we're using a nexus 4 DDR and it has an Arctic 7 FPGA and we could specify that by changing the family we also have knowledge of the package which is a CSG 3 to 4 that just means that the FPGA that we're targeting has 324 pins the speed grade of the Nexus 4 ddr's FPGA is minus 1 and it doesn't actually have a specific temp grade this is a temperature grade for example if the embedded application was to operate in harsh environments so there are 5 options left available the if you look very carefully at the Nexus 4 ddr's FPGA chip you'll see that the particular model number is x c 7 a 100 t CS g 3 - 4 - 1 the only difference between the 5 available options is the amount of resources on the FPGA itself once you've finished you just have to make sure that all the information you've put in is correct and then hit finish ok so now that we've created our project we're presented with the Vivaro integrated design environment on the right here we have the project summary and this just provides us with some basic information about our project on the Left we have our sources we haven't got anything here yet because we haven't specified anything but design sources is where our very log files that describe our hardware will be constraints will be where we store our constraints file and of course our simulation sources directory will be where we store anything related to simulation down the bottom here we have some other useful information including a console but what's really really important down here is the messages tab which is where our errors and warnings and other useful information will appear during our designs and also reports so once we in synthesize our design and implement it we'll be able to access you know useful information regarding things like resource usage power consumption and also timing resources so this reports tab can be very very useful when we start working with more complicated designs on the very far left we have what is called the flow navigator this flow so it follows the typical design flow for FPGA development where basically we can add sources access language templates or even access silencers IP catalog which is basically just a library of pre-existing modules that you can implement in your designs we're not really going to worry with IP integrator too much or RTL analysis but these are useful tools for creating code using block diagrams or exploring how Xilinx actually interprets your design in terms of logic functions so typically what happens in you know FPGA development is you created a design sauce and then you'll simulate it and so you know when we simulate it we're just checking that the behavior is as expected once we're finished with running our simulations will run synthesis implementation and then if everything is correct and everything is fine we'll then go ahead and generate what is called a bit stream so synthesis is important because it translates whatever code you write into you know load it functions and so you know we don't we don't call it compiling in this case we call it synthesis however I will use the terms interchangeably but we're not compiling a program in the context of software development we're synthesizing a design and so the code that we write describes the behavior of the hardware the actual FPGA and when we synthesize it it's translating your code into a logic equivalent implementation is important because once it takes once the design has been synthesized it then has to be placed and routed on the physical FPGA and implementation is where it's very very important that you specify the correct project part if for example we were targeting the Nexus for DDR but you had an incorrect project part so let's say we were targeting a smaller FPGA then it's the implementation tools wouldn't be able to well if you try it would implement it but then when you when it came time to target your particular FPGA with it it would be expecting a completely different chip and so it wouldn't work and that's why it's absolutely crucial that you make sure that this is the correct model number the generate bit stream is the final step in in the design process this is what converts all of your work into a single file that is then downloaded onto the FPGA to program it so the first thing we're going to do is create a design source so you can go ahead and right click on design sources and go add sources your represented with this window and you can create or add constraints design sources or simulation sources we're going to start with creating a design source so when we get to this window you'll notice that there's a couple of options add files directories or create file we don't have any existing source file so we're just going to create our file from scratch the window that pops up will ask you to specify a file type in this case we're using very log we will not be using VHDL during this course and the other two options are no not really that important to understand right now except system very log which is a superset of very log the name of our source in this project is going to be switch to led and I always change the profile location to somewhere you know reasonable I don't like storing files local to my project just because it's harder for me to keep track of them so I'm gonna store my design sources in this directory FPGA and then a subdirectory called sources so once we've created our file we can go finish and another window will pop up which allows us to define our module so this is where we can declare inputs and outputs to the module and in this case what we're doing is designing a an FPGA program that will illuminate an LED when we activate a slide switch so I'm gonna create a port name called slide switch and it's an input and it's a single bit so I don't need to declare a bus and then I'm going to declare an output and I'm gonna call that LED once you've declared all your i/o ports for that module you can go ahead and click OK so you'll notice up here in sources that switch to LED TV has appeared under design sources if you double-click on that it'll open up in the text editor so the file that appears starting from the top has this line here that says timescale 1 NS / 1p s this isn't really relevant right now this is useful for simulation but for now we can ignore it the lines that follow are just file information so you can put in for example your name here you could put your company you could put a whole bunch of oh crap but right now I actually think it's more of a distraction so I'm gonna delete it okay so what we've got here is a module declaration and so this module keyword basically says that the following code is a module and it's called switch to led for some reason our output is missing but I can just add it in like this and it was called LED but this just declares the different inputs and outputs of our module because we're creating a light switch there's only one input slide switch and there's only one output LED okay so this is where we start describing the physical behavior of the FPGA what we're doing in this design is essentially creating a wire between the slide switch and the LED through the FPGA chip and the way that we're going to do this is to basically assign LED to be equal to whatever slide switch is now that we've done that if we went to compile this design or synthesized this design if nothing would work and the reason for that is that we haven't told the synthesis tools wheres light switch is or where LED is and so it's important for us now to do what's called constraining our design and so what we'll do is we'll quickly create a constraints file so we don't have an existing constraints file so we're just going to create one the file type is xdc it stands for Xilinx design constraint and the file name will be something useful so switch to led nexus for DDR constraints the reason this is such a detailed name is because the constraints file really does belong to a project and it also definitely belongs to the particular board that you're targeting so I'm gonna also go ahead and save this file into my constraints directory okay we'll finish you'll now notice that a constraints file has appeared under the constraints directory if you double click on that it'll open it up but there will be no information in it so the thing with constraints files is that they define or they at least they inform the synthesis and implementation tools about where different signals are coming in and out of the FPGA so on the bottom of the FPGA there are 324 pins on this particular one and what's important for us is to to route the slide switch which have to figure out which pin that connects to on the FPGA and then also figure out what pin and assign the pin of the led so this this is a little bit you know tricky but what we need to do is basically set some properties for these signals and so what we're effectively doing is connecting our slide switch and our led up to physical pins on the FPGA so the way we do this is using a constraints file in this particular case the language is called tickle and it's a command based language which basically means that we we set commands so I'm gonna set the property of what is called a packaged pin and if you look closely at the Nexus for DDI you'll notice that it is the slight switch is connected to pin j1 v and what we can do is actually just connect that into slide switch using this code here so set property is the command the property that we're setting is the packaged pin the value that we're assigning that but he is j15 and then this next bit here everything inside square brackets in tickle is interpreted as a function so this function get ports is going to search our top-level module which in this case is switch to LED for signals or inputs and outputs called slide switch and so you can see that the the input here is slide switch so that's fine so we can also do the same thing for the LED except now the LED if you look at the data sheet is connected to pin h17 and of course it's called LED excellent okay so we've set the pin locations for both the switch and the LED but now we have to do something else and that is to set what is called an i/o standard and the reason why this is important is because the FPGA is going to interpret whatever voltages it receives using de various CMOS or LVDS standards so we can see from the datasheet that the slide switch is actually connected to a 3.3 volt power rail and what that means is that when the slide switch is in the on position it will connect a 3.3 volt signal into the input pin and then when it's in the off position it will be pulled down to ground so what we can do is set the property and it's called IO standard to lvcmos 3:3 and that stands for low voltage CMOS 33 and then of course we'll apply this function get ports to slide switch now we're done all the information that is required in order to connect our design to that particular slide switch is complete the last thing we need to do is specify the aiyyo aiyyo standard for the led and this is a little bit more complicated because it's not an input which means we're not informing the implementation tools what kind of voltage to expect instead we're really informing it what kind of what voltage standard we want it to drive at so if you look at the data sheet you'll notice that there a node connected resistors just after the LED and the reason these resistors are there is because LEDs are non ohmic that just means they have effectively no resistance so if we were to drive the LED with any voltage without any a node connected resistor then the amount of current drawn by that circuit would be huge you can resolve that in your head by thinking of Ohm's law which is V equals IR and therefore the current I is equal to the voltage divided by the resistance and if the resistance is very low then the current will be very very high so there's a resistor there and in this particular design it is a 330 ohm resistor the reason it has that particular value is because it's trying to limit the current that can flow through that circuit to within the acceptable range of the LED so in this case the LED can accept probably between well anywhere up to about 20 milliamps so we can get away with setting the IO standard of the led to lvcmos 3:3 which will generate a 3.3 volt signal on the output of the FPGA and then if you divide 3.3 volts by 330 ohms you'll really you know end up with a result of 10 milliamps and so that is why when you're setting the IO standard of an output you have to you know actually think about it you can't just look at the data sheet and see what rail that's connected to you could for example connect the LED up with a 1.8 volt signal or a 2.5 volt signal or 5 volt signal it's not really a problem but you should think about what that would mean in terms of the brightness of the LED you know if we put more voltage onto it then we'd be allowing more current to flow and you would think that the LED would therefore be a little bit brighter okay so now that everything's finished it looks like we are ready to generate a bit stream okay so I'm just checking the code to make sure that there are no obvious issues we've got one input called slide switch we've got one output called LED all of our set properties in the constraints file are correct okay it looks like we're ready to basically run synthesis so synthesizing this design is trivial because we're legitimately just producing a wire so we're we're we're telling the FPGA I know that you're really fancy but really all I want you to do is give me a physical wire connection from this pin j15 to this other pin h17 and the synthesizers not going to have a lot of difficulty achieving that but we'll wait for it nonetheless excellent so synthesis is now completed and you know there's a couple of options that you can select here but we're just going to go ahead and run implementation so you'll notice here in the messages window down the bottom that two warnings have popped up and I'm going to quickly look at them just to make sure I know what they are okay so design switch to LED has an empty top module I'm not sure why this pops up but it's probably to do with the fact that we only have one module in the entire design and that module is called switch to led if we had more modules than what we would be able to do is right-click and it's grayed out now but we could set as top and what that does is says it says to the implementation tools this is the top module and that's important because when the implementation tools come along and try to connect physical inputs and outputs in the top module two pins on the FPGA it's going to look at whatever is declared as the top module so right now you can see at the top right we have a current status of what's actually going on the implementation tools haven't thrown any warnings at this point but running router design what this is actually doing is now figuring out how to create a wire from pin j15 to pin h17 and it obviously didn't have too much difficulty doing that if it did I'd be very concerned okay so the options here we can open our implemented design or we can generate a bit stream so I'm just gonna go straight ahead and generate a bit stream by the way you don't need to really worry about these options here the launch runs on localhost it's it's basically saying you know just run four parallel tasks on this particular computer but you know you don't need to wipe out any of the other options okay so now it's currently writing the bit stream and this is the the good part because it produces a file called a bit stream it'll be it'll have the file extension doc bit and that is the file that we will end up programming our fpga with and it doesn't fortunately take very long to do so in this case I expected the the longest part of the of the of the build process to be implementation but really you know for more complicated designs synthesis could be you know take quite a while but generally implementation is what takes the most time okay so bitstream generation has successfully completed this is good the options that are available to us we don't need to worry about them too much but if you wanted to actually look at the the actual design that Vivaro has all that the the routing tools have figured out through the FPGA you could open the implemented design you can also view reports but we can also do that from the bottom menu here you can also generate a memory configuration file don't worry about that right now and what we are actually going to do is because we just want to program our board straight away we're gonna open the hardware manager okay so you'll notice that the window has changed now so we are now connected to all opened into hardware manager and what we need to do to start with is open a target so this is where you need to make sure that you have a USB connection between your fpga board and your computer if you're using a nexus for ddr or a basis 3 then you want to make sure that the device is powered on as well once you've done that just select open target and then hit auto connect and what this will do is establish a connection to your fpga board i think it is creating a like an like an Ethernet of a USB connection localhost is the computer and then the Xilinx underscore TCF is the actual board okay so this is good this means that we have a connection between the computer and the board now all that's left to do is to program the device so really at this stage everything's looking fantastic you just need to make sure that it's going to load the correct bit stream file so in this case because our top module is called switch to led the bits the bit file is called the same thing except the file extension is different the file extension is dog bit so once you've checked that files correct you can go ahead and program your device you should notice when you do this that whatever default program was running when you first turned the nexus 4 board on will stop it'll cease and now if you flick that LED on it'll turn on and that is essentially the most over-engineered light switch you will ever design in your life thank you

Channel: FPGA Therapy

Views: 39,551

Rating: 4.9732976 out of 5

Keywords: FPGA, Vivado, Xilinx, Verilog, HDL, Getting Started, Project, Nexys4-DDR, Nexys4, Basys3, Digilent, Constraints

Id: BBtD4PCXqlE

Length: 27min 22sec (1642 seconds)

Published: Thu Feb 22 2018