Creating a custom AXI-Streaming IP in Vivado

[Music] hi I'm Jeff Johnson FPGA developer in this video we're going to create a custom access streaming IP and Vivaro access streaming ip's are useful when you have to do some kind of processing to a stream of data such as samples coming from an ADC or images coming from a camera we're going to build an IP with both a slave and a master access streaming interface I could also say an input and an output interface the custom IP is going to be written in very log to test out the IP we're going to use a DMA to push data into our custom IP and to pull data back out of it to keep the code simple the custom idea will just buffer the input data and make it available at the master interface in other words we've been making an access streaming FIFO so this block diagram shows what we're going to put together in Vivaro the Zink processor system will need a general-purpose AXI master interface for controlling the DMA it will also need a high performance access slave interface so that the DMA can access the DDR memory then on the other side of the DMA we've got our custom access streaming IP ok so let's get started first we create the project now we're going to name this micro Z custom access streaming IP click Next it's an RTL project with no code now I want to set this up for the micro said 7010 board so the first thing we do is create a block design now in the block designer we've got to press the plus button and add our sync processing system and then of course we've got to apply the board preset by clicking on run block automation now we're going to create custom IP by using the create and package new IP we're going to create a new XE for peripheral now here we're going to set up the name of the peripheral to be Axios fifo now in this window here we get to set up the interfaces that we want using the plus and minus button we can add more interfaces or delete interfaces now I've just added two interfaces I want them both to be access streaming interfaces and I want one of them to be a master and the other to be a slave then I'll delete the first one that was there by default then I can click Next and I want to edit the IP so I'll click on edit the IP and that will open up a new Vivaro window that allows me to make modifications to the IP now the IP packager will generate code to drive each of the interfaces that you created in the previous window you can see those files up in the project manager it's worthwhile taking a look at the code in those files you might find it useful in this example we're actually going to overwrite the generated code and replace it with code for our access streaming FIFO the code part of the exe streaming FIFO comes from Alex foreign and such you can find it on his github repo we're going to use a slightly modified version of that ax C streaming FIFO and I'll post it below the video so here I'm just selecting all the code and pasting over it with the new code here's a quick look at the code you can see it has an ACCI streaming slave and a master interface now when we save the file you'll see that the auto-generated modules for the slave and master interface are no longer part of the hierarchy because they're not getting instantiated by the top file anymore so now we just have to click review and package and repackage the IP and I want to close the the Vivaro window by clicking yes now the zinc processing system has to be reconfigured so that I have a general-purpose accent master interface so that I can control the DMA and I also need access to the DDR memory so I need to enable a high-performance access slave port and I'm just going to check my clock configuration so I know I can see here I've got a hundred megahertz clock being generated it's one of the fabric clocks and lastly I'm going to enable interrupts from the fabric so that my DMA can pass interrupts through to the processing system now I'm going to connect up my clock the fabric clock the hundred megahertz fabric clock I'm going to use it for both of my XE interfaces now I'm going to add my con cap which is going to be used for the interrupt so I'm going to have two interrupts to connect from the DMA now I can add my DMA now I'm going to use the connection automation to connect up my exit light interface and the high performance access slave of the processing system so the DMA actually has three interfaces that need to go through to the high performance access slave interface so it's going to create the automation features going to create a an acci smart connector or an interconnect in order to route these three interfaces through to the DDR so I just ran connection automation again for the last two interfaces now I notice I've got my status and control ports that I don't need so I'm going to double click on the accidie MA and I'm going to untie control status stream because I don't need those ports there for Ethernet designs now I'm going to hook up my interrupts through to the concat and now I'm pretty much ready to add my custom access streaming FIFO to the design so I find it now in the IP catalog now I'm going to hook up the AXI streaming interfaces to the DMA and I'm going to use the connection automation to look up my AXI streaming clocks and resets I'll save the block design now I've got to create a top top-level HDL wrapper you you can ignore these critical warning messages there due to the micro said board preset I'll leave a link and explanation in the notes below the video so then I generate bid stream and then once the bitstream has been generated I want to export hardware and include the bitstream now I'm exporting that to the SDK so now once that's done I can launch the SDK I'm going to do it local to the project so the first thing the SDK does is load in the hardware platform specification your exported hardware design so that should be the only thing in the workspace now I'm going to do a new application project and I'm going to do a hello world application to start with just so that I can test my hardware and make sure that I've got everything running properly that my bitstream is good that my you white connection is good and then once that's working then I'll do then I'll test my actual custom IP so I just plug in my USB you are to the computer and I see that the micro zip powers up I open up my UI console now I know what comport the my micro said loads up on my computer if you don't know what your one does you'll have to go into device manager and find it and figure it out you know I'm going to load the bitstream program the FPGA and then when that's done I see the FPGA done the blue FPGA done LED light up no one are going to run configuration so that I can run my HelloWorld application and when I run it I can see that my UI console has hello world written in it so I know that the application run correctly so now what I'm doing is I'm making a new another application project but this time it's going to be the one to test my FIFO I'm going to create an empty application because I'm going to add my own code to it so to test the application I'm going to use an example DMA test application that Xilinx provides you'll find it in the Xilinx installation in the Vivaro installation files or actually the the Xilinx sdk installation files it's along with the driver for the acts of DMA in a folder called examples now I'm dragging and dropping the file called X accidie ma example s gee-pole so this example code what that does is it tests out the DMA by sending or making the DMA send data out through the streaming interface and then reading what comes back through the streaming through the other streaming interface and comparing the two so if we have hook those up in look back or if you put them through an access framing FIFO and look back then you should the application will pass because the the data that sent out is equal to the data that was received so now to run our application we have to first select the FIFO test application and then we go into run configurations then in run configurations we have to double click on system debugger and then we can click run now of course we'll have to terminate the hello world application first so we click yes and when our application runs and it has run we can see in the UI console that it has successfully run so the DMA has been tested as has our custom IP

Channel: FPGA Developer

Views: 28,146

Rating: 4.9004974 out of 5

Keywords: microzed, vivado, dma, custom ip

Id: R8MSpEU7UKE

Length: 14min 27sec (867 seconds)

Published: Tue Oct 31 2017