Using the Vivado Timing Constraint Wizard

hello and welcome to this quick tech video where you will learn about the timing constraints wizard we'll start with a high-level overview of the tool what it does and who would use it then we'll follow that with a few animations of how the wizard works and finally we'll launch from avato and show you how the wizard operates on a real design so let's get started the timing constraints wizard is a new feature available in our 2014 dot 1 software release that assists you in the process of creating timing constraints for the novice user it is very quick method of creating an initial xdc file in the process of doing that you'll learn our timing methodology and the tickle commands used to constrain the design for the advance user the wizard can be used to verify the coverage of your constraints and as you will see shortly the timing constraint wizard performs a very thorough analysis of your clock domain crossings that I'm certain that you will find very useful to help Movado converge you design quickly you need complete and accurate constraints the timing constraint wizard was created to completely constrain your design in the demo I'll show you check timing results before and after the wizard runs to illustrate this point but the other half the problem is yours it's critical that you provide accurate constraints if you over constrain Vivaro you'll increase run time and divert its attention from real timing issues if you under constraint vivre Auto then report timing will pass but your board may not work at your target frequency finally you need to be diligent in updating your constraints as your design solidifies usually you'll start with some abstract performance metrics these can usually be translated into a first pass set of constraints but as your algorithm solidifies and your boards design solidifies these numbers will need to be revisited your constraints need to evolve as your design converges the other thing I'd like to mention is that the timing constraints wizard follows our ultra-fast design methodology our methodology starts by having you define all the clocks that exist in your design you then specify the interactions between these clocks next you can strain all your inputs and outputs and finally you cautiously and sparingly add timing exceptions such as false paths and multi cycle paths it does slightly adjust the order of the i/o constraints and the clock interactions but as you will see this apparent discrepancy can easily be resolved so with that being said let's go ahead and show you how the wizard works to determine clocks in your design the wizard starts at every sequential element in your design and traces the clock back to its source for example in its design the wizard starts at the flop traces backwards along the highlighted path and eventually arrives at the primary input at that point the wizard looks to see if a constraint already exists on this input if it does then it will not recommend a constraint but in this case for the clock five input no constraint exists and therefore the wizard suggests a create clock constraint and prompts you for its frequency when you proceed to the next page of the wizard the clock is created in the in memory design and is used for the next analysis the wizard then analyzes the design looking for clock interactions in this case the wizard sees the mocks between o'clock four o'clock five these are logically exclusive clocks since only one of the two clocks can propagate through the mocks at a time the wizard suggests adding a logically exclusive clock group between clock 4 and clock 5 finally the wizard looks for all the inputs and outputs captured or launched by clock 5 if these are not constrained then the wizard will suggest a constraint in this case the MUX select and the two inputs require constraints relative to clock 5 you can choose which timing template you want to use to specify the constraint and provide the accurate values the wizard first defined the clocks then define as clock interactions and finally constrain the iOS let's move on to a demo where I can show you some of the capabilities and features of the wizard here I have an example project open the timing constraint wizard operates on a gate level netlist in this case synthesis has already been completed so we can go ahead and open the synthesized design let's start by taking a quick look at the existing constraints file we see a few definitions for primary clocks in the design one thing that I see here is that we have two clocks created on the same port these are likely physically exclusive clocks I also see a lot of input and help with delays there's also a set max delay constraint between sis clock and clock 83 this constrains the clock crossing paths between these two clocks finally SEL falls paths on the clock select at the bottom of the file since I'm not too familiar with this design let's start by running report timing a summary as you can see here we are not passing timing we're failing by about 8.3 nanoseconds also if I expand the check timing category we have several issues we have a category for no clocks unconstraint internal endpoints missing i/o delays some multiple clock issues and finally a few unexpanded o clocks our hope is that the wizard will clean all of these up let's also look at the clock interactions a run report clock interaction to gain some visibility into the clock domain crossings the first thing that I noticed here is that we have some unsaved clock crossings down here in the lower left corner we see the sis clock - clock 83 clock domain crossing that was constrained with the set max delay - data path only tickle command we saw this earlier in the XTC let's go ahead and start the timing constraints wizard and see if we can address these issues from the flow navigator I can click on the constraints wizard it looks like I don't have a target constraint file set in this project so let's go ahead and create an empty one I'll first select add sources from the flow navigator I want to create a constraint so I'll leave the default and click Next let's call this top dot xdc and I'll click finish it looks like the synthesized design needs to be updated let's go ahead and do that now you can clearly see the top that ecstasy in this horse's view but for the wizard to run the warning said it needs to be set as target and the processing order needs to be normal I can settle this target by right-clicking on the file and choosing set as target in the properties tab you can see that the order is already set to normal let's go ahead and try the wizard again the introductory page the wizard has a lot of useful information and I encourage you to read it thoroughly but for now let's go ahead and skip it this is the primary clocks page of the wizard and it looks like it has identified two clock inputs that are missing constraints I know that clock 100 and clock 166 are 100 megahertz and 166 megahertz respectively that translates into a period of 10 and 6.02 four and an O seconds as I enter the values above you can see the tickle commands updated in the preview pane below there are a few things I'd like to point out here before I move on to the next page on the bottom left corner of the wizard there's a reference button these are on every page the wizard and should help explain what the wizard is doing here it has a description of what the clock is the tickle command used to generate the clock and the tickle command reference allowing you to see all the options for the create clock command to the left of the table I have a toolbar the first button allows me to search for a particular signal it's obviously not that useful in this design the next two icons allow me to select all of the recommended constraints and enter the same value for all of them if I enter a hundred megahertz then both clocks are set to the same frequency for now let's go ahead and change this back to 166 the last toolbar button allows me to generate a clock Network report here you can see the clocks that are already existing in the design as well as the two clocks we are about to constrain the cue clock pin will be constrained later in the wizard to show you how the wizard issues tickle commands real time I'm going to open the constraint editor in the background when I press the next in the wizard the tickle commands are issued in the in-memory design so they can be used for future analysis the wizard notice that we have a generative clock in a design and is prompting for a / value in this design I have already looked at the circuit and I know it's a divided by two so I'll enter two and move on a forwarded clock is a generated clock definition and an output port these are commonly used for source synchronous buses let's look at the schematic to see if we can understand the motivation for this constraint even though the wizard is open we can still access the main of of Auto window this looks like a typical source synchronous bus the clock that records the data in parallel launches the capture clock in this case the flop is non-inverting and the wizard correctly detected the relationship between the forded clock and the source clock next the wizard looks for any external feedback delays of your MMC ms these are used as compensation for internal PLL's i'll use point 5 and 1 for the min and Max external delays here we see all the inputs to the design that are unconstrained if I wanted to I could skip the input section by unselecting all the recommended constraints and hitting next this would allow me to proceed to defining the clock interactions before I spent too much time on the iOS for this demo though we'll proceed linearly through the wizard on the bottom of the wizard you can see the waveform that matches the template above if I change the timing template then the waveform updates appropriately I can enter the values for each constraint in the box on the right once I have entered all the values I can apply them this will run a quick validation to see if there are any errors there's a filter on the left-hand side that allows me to see constraints that I've already entered that are valid ones that I've entered that have errors and rows that I have remaining to do let me fill in the remaining values and proceed with the next page similar to your inputs for the outputs we select the templates and then fill in the values in this case I know that the SSD out port is a source synchronous output and I'll change the template as such let me fill in all these values again if you wanted to add the output constraints later you could uncheck all of the constraints and hit next here we see the combinational paths for the FPGA these are paths that enter and exit the FPGA without interacting with any sequential elements to constrain these you could use a set Max or set min delay constraint but instead to keep consistent with the other iOS we define a virtual clock and then set all the input delays and output delays relative to that virtual clock let's change a virtual clock period to 10 nanoseconds now I have a choice I can either enter all of these values one of the time or since I know that these are all the same I can use the multi row edit first I select all the constraints then I press the pencil button to edit them all at once here we can see the physically exclusive clocks that the woods were detected in the design these are the clocks that we saw in the ecstasy earlier so that's only one of these clocks can be active at a time the wizard suggests we create a physically exclusive clock group we agree with this analysis so we'll continue logically exclusive clock groups usually occur when you have a MOX between two aux the MUX only allows one of the clocks to propagate in the case when there are no timing paths between the input clocks the MUX and a clock exiting the MUX then we suggest a logically exclusive clock group we'll accept this constraint in the case when there is interaction between the input clocks and the clock propagating through the MUX then the wizard will create two generative clocks at the output of the MUX and set them logically exclusive I'll accept this constraint and move on clock domain crossings are usually difficult to analyze this page looks at all the asynchronous clock crossings in the design in the top table we see some clock domain crossings that the wizard is suggesting we add constraints the wizard is listing the source the destination the number of paths between the two o'clock domains the number of paths that are properly synchronized with the asynchronous reg property the number of paths that are synchronized but are missing the asynchronous reg property the number of paths that are not synchronized and finally the number of paths that are already constrained by a set max delay - data path only constraint in this case we have four clock domain crossings that the wizard is suggesting constraints for in each of these cases we are missing the asynchronous reg property in the design we strongly encourage you to set this property to ensure the proper placement of these registers if you want to see one of these paths we can click on the link in the upper table and then the lower table it will list all the individual paths between the two clock domains it will also show you the depth of the synchronizer I can then select one of these paths and hit the schematic button to see the exact c-d-c in the schematic I can expand that schematic to see the synchronizer the table in the center lists all of the clock domain crossings that the wizard is not able to make suggestions for in this case we have one clock domain crossing that is not synchronized and needs attention in RTL and we have another one that's already constrained now that we're happy with all the cdc's we can go ahead and click next the wizard summarizes all of the constraints that were created you can review them by clicking on the links finally it a skew if you would like to run any additional reports once the wizard has completed we'll go ahead and run the report timing summary again if we take a quick look at our target XTC it's still empty it's important to remember that the wizard is working on the in-memory design if you want to save your constraints the target X you see you must hit the Save button in the main Vlado toolbar if we then reload the target X you see you will see all the constraints that were generated by the wizard as you can see in the report timing summary we are now passing timing and if you expand the check timing we have only two warnings one is warning us that we have an input that is false path which is correct because we saw that in the original XTC the second warning says we have an output pin with no output constraint but in this case we have a generated clock on that output pin for our source synchronous bus both of these warnings can be ignored and the constraints are looking pretty clean let's run one final report to check the clock interactions as you can see here we have a lot more clocks in the design than when we started the wizard identified two missing clocks and a few generated clocks and it also created a few virtual clocks while it was constraining the design all of the dark blue boxes are constraints that the wizard added we still have the light blue box in the lower left-hand corner which is from the original xdc file and we also have one red box that indicates an unsafe crossing the wizard actually detected both of these and warned us about them in the middle table on the CDC page we'll have to go edit the RTL to fix this as you can see we started with a design that had lots of issues the wizard has done a great job at full Ekans this design so let's go ahead and summarize so that you have learned today is that the timing constraints wizard simplifies constraint creation and validation it adheres the ultra-fast design methodology and you've seen an example that started off with poor constraints that actually ended up fully constrained after running the wizard if you'd like more information we have comprehensive avato courses available at the web address listed we also have three user guides that it would be extremely useful with regards to timing constraints and finally if you have specific questions you're always welcome to post them to our developer forums with that I'd like to say thank you for watching this video about the timing constraints wizard you can follow us on facebook twitter or watch more of quick dick videos on youtube thank you

Channel: XilinxInc

Views: 25,974

Rating: 4.744 out of 5

Keywords: ultrafast, vivado, timing constraints, constraining timing, defining clocks, clock interactions, input constraints, output constraints

Id: UmQ0PUEaOuk

Length: 18min 13sec (1093 seconds)

Published: Fri Apr 11 2014