RISC vs CISC - Is it Still a Thing?

hello my name is Gary Sims and this is Gary explains now in the comments section below some of my recent videos people have been talking about Sisk and risk so that's complex instruction set computing and reduce instruction set computing and they would say think about all that's because it's Sisk and they were probably referring to x86 well that's because it's risk and they were probably referring to arm or to risk 5 and it got me thinking is risk versus Sisk still a thing so if you want to find out more please let me explain so let's just define some terms and get a bit of history Sisk stands for complex instruction set computing risk for reduced instruction set computing and the idea is up until about the 1980s most computer processors the CPUs were getting more more complicated and the idea was was that if you could make the hardware sort of mirror what the software does then of course it would be quicker so as you wrote a program in the course in those days that have been probably exclusively in C or Fortran as you wrote a program in those if it starts to produce some instructions if those instructions could be executed more and more in the hardware with less and less instructions that would make the whole thing go faster and there were also other considerations like memory was expensive so if you had shorter program that each instruction could do more complicated things that would be better and also you know the speed of memory was different and of course the complexity of you know processes themselves a number of transistors was also very different in those days and then in the early 1980s this idea came along of well let's have a reduced complexity and that kind of got called reduced instruction set computers although actually as we'll see in a minute it's not really about having a smaller number of instructions it's more about how you use those instructions now the argument was put forward like this if you can have a less complicated of instructions then designing a CPU will be easier and if it's easier it'll therefore be cheaper and if it's cheaper and easier it'll also happen quicker and one of the fundamental ideas behind this was that every instruction can be executed once per cycle so we talked about clock speed oh my see is clocked at 2.2 gigahertz or 1.3 gigahertz and so every time that kind of wave of the frequency happens you can execute one instruction that's the idea and any a complex instruction computer that's hard because each instruction is doing so many things you have to wait two three four or five maybe more cycles for it to get round to do all those things go into in a RISC set up the idea is that every time you execute a cycle you can actually execute an instruction so once you start to think along the lines of one instructions per cycle there are some other assumptions that you can make and I'm really talking about some of the things that David Patterson wrote when he proposed the idea for the RISC one and the risk to proces we found a similar thing in kind of the MIPS processors that were being developed also in that same time frame one is as I said that you execute one instruction per cycle another is that the instructions actually have a fixed size in memory and that means that it's easy to decode them and easy to kind of send them down towards the pipeline into the execution because you're dealing with the same fixed amount of data in something like x86 the instructions can actually be variable length up to I believe 15 bytes long and you don't know how many bytes are related to this instruction until you read the first bit of the instruction and then see what you need to read on afterwards when you have a fixed instruction size you can always take the same block and you can very quickly process it because you know exactly what you're grabbing it each time and probably the most fundamental difference about risk versus sisk is that risk does not do any operations directly on memory what I mean by that if you for example have the number 7 in address 100 in memory and you want to add one to it in x86 and other Sisk kind of instruction sets you can say add one to the number that is in address 100 now to do that the CPU first of all has to go in fetch what's in address 100 and bring it into the CPU it then has to add one to it and it then has to write it back out again and it does all that following just one machine code instruction that it read but it obviously has to do three separate things the fetch the add and then the putback now with risk what you actually have to do is you have to have three instructions and first instruction says go and fix that memory the second instruction is add one to this register where that memory contents was placed and the third instruction says please write that back out now to the main memory so what would be one instruction in the complex instruction set computer with three instructions on a RISC computer and the idea being that each one of those instructions can be executed every cycle so because they're small enough because they're reduced enough because they're simple enough you can execute one every cycle and you don't have to worry about trying to work out what all these other things I have to do to get this thing to actually complete and because of that of course it means the compiler plays a much bigger role how the optimization happens is much more down to the the way the instructions are kind of put into the program by the compiler so you might run a program in C or in Fortran or today in other more modern languages but actually how the compiler produces that set of instructions is vital to gain the great performance or the better performance out of the of a RISC computer and because you have this idea of trying to execute one instruction per cycle we then also have the concept of a pipeline where the instructions start to be processed to be decoded and the different internal states start to be modified and as it goes down the pipeline then finally the instruction is executing the original RISC would have a very short pipeline maybe even two stages and because of that to deal with the whole issue of branching what happened in the CPU jumps off somewhere else they actually had the idea of a delayed jump what that means is that when the the instruction was executed the next instruction was already coming down the pipeline so what they liked is after a jump you actually had a no op or an op operation which did nothing so that when you finally did branch somewhere else that last instruction that was already kind of hot on the heels of the jump instruction doesn't affect the the outcome of the program in fact they actually said you could actually optimize it in the sense that you could have two jump instruction first and because you knew the next instruction was already coming up behind you it could be the last instruction that you wanted to have for the jump happened so actually you wrote jump first then the last instruction they would both get sucked into the pipeline then the jump would cause it to go off somewhere else but that last instruction would still get executed so the idea of a delayed jump and so this will all work that kind of happened in the in the 1980s and into the 1990s and you've got this difference between risk and sis now a lot of people will make comments like yeah but the 90 showed us that risk lost and a sisk one and they're probably talking about maybe let's say servers for example or our desktop PCs because they all use 86 cause that's nonsense for two very important reasons one of course we all use risk processes all the time in our smartphones in Chromebooks in tablets okay so sis process have been absolutely vital of what we do absolutely every single day but also people forget that the world isn't just divided into x86 and arm take the example of IBM for example all that stuff is doing with that what's an AI that can play all these different games and it can do all that really clever stuff well they're using the power architecture which actually is a risk based architecture so risk in servers risk in phones is very much here it's only because of the dominance of x86 in the desktop a world that actually people think that everything in the world important is actually Sisk that's far from the truth so is the Cisco and RISC thing really an issue today well if we take the context of what actually happened during the 80s and 90s you could remember things at this back then patterson wrote like well you've only got a million transistors and we really should be using those million transistors for kind of making an efficient pipeline for executing lots of small instructions rather than wasting it on making big complicated instructions of course that was a million transistors that was back then today even an SOC like the Kiran 980 it's got six point nine billion transistors in it so we've really shifted our whole kind of view point about what makes up a processor where that's a CPU or a CPU and a GPU and all the other stuff put together we really are a magnitude different today in what we had back when the whole Sisk risk thing started and everything it was interesting is that back then the idea of a branch predictor was seen as a kind of an elaborate technique something wasn't really going to give much results in terms of performance course nowadays all of the major processes whether on the desktop whether it's in your Chromebook whether it's in your smartphone has got branch predictors in them and the idea that the program tries to look ahead maybe even ten twenty instructions ahead to see whether there's a branch coming up and then structure to predict when that branch will take the program into one direction or another so the instructions can keep on coming down the pipeline without a bubble without a gap in that pipeline that's standard practice nowadays so that wasn't standard practice back then but it is now but he's a thing that a lot of people don't understand starting with the Pentium Pro Intel actually changed the way they designed their processors and they had this idea of this thing called a micro opt so when it sees an instruction that says like add one to this address in memory it breaks it down into three separate instructions and sends those instructions down the pipeline well you might think hold on you said in risk it was three instructions that go down the pipeline exactly so today actually a lot of sis computers actually break down those complicated commands into RISC instructions than those risk instructions are actually sent down the pipeline and so Intel has been doing that now for a long long time and that's the basis of what it how it builds its CPUs of course to do that because it's got hasn't got fixed length instructions got complex variable instructions it has a lot of logic at the very beginning of the chip that actually looks at the instructions that are coming down and then kind of in a brute force way decodes them splits them down into these micro operations and that's why x86 has struggled to be successful in smartphones because that extra logic at the beginning that extra transistors that produce extra heat and use extra power to split those instructions down into risk types instructions then send them down the pipeline is enough to mean they're not as power efficient as the equivalent arm processors okay my knife carry sim this is Gary explained I really hope you liked this video please do give it a thumbs up please don't forget to subscribe and well that's it I'll see you in the next one

Channel: Gary Explains

Views: 129,051

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Keywords: Gary Explains, Tech, Explanation, Tutorial, RISC, CISC, CPU, Pipeline, RISC-I, RISC-II, RISC-V, David Patterson, Complex instruction set computer, Reduced instruction set computer, MIPS, x86, x86-64, Intel, Arm, POWER9, IBM, IBM POWER, IBM WATSON, WATSON, Berkeley, University of California

Id: g16wZWKcao4

Length: 11min 17sec (677 seconds)

Published: Fri Mar 08 2019