Introduction to FPGA Part 2 - Getting Started with Yosys, IceStorm, and Apio | Digi-Key Electronics

previously we talked about what an fpga is and what it's good for before we get our hands dirty with verilog we need to install the tool chain lucky for us there are free and open source tools that work with the fpga on our dev board let's get started [Music] if you head to yosishq.net you can learn about these tools the yosis tool synthesizes verilog rtl code note that it specifically supports the 2005 version of verilog so that's what we're going to use if you check the faq you can see the different fpga targets that it supports we'll be using a lattice ice 40. click on next pnr and you'll be taken to a github page here you can see a visualization of how next pnr works it's quite literally making connections between cells in the fpga the output of the place and route step then goes to tools in the project ice storm suite scroll down and you can read about the individual tools we'll be using ice pack to convert the ascii output of the pnr tool to a binary that's readable by the fpga finally iceprog uploads the binary file to the fpga to make life easier we're going to use appio this is a tool that manages all of the tools we just looked at it provides methods for installing them on all of the major operating systems through python it also comes with a number of examples that can be good starting points however note that where the tools can be made to work with just the chips on custom boards appio is really intended to support various development boards that you can buy if you do make a custom development board i'm sure you can do a pull request to have it supported in appio i also want to point out this ice studio project ice studio is a block-based coding environment for verilog you can see it in action in some of these gifs it runs appio and the other tools we saw earlier in the background so it only supports lattice ice 40 chips at the moment for now i want to stick with verilog and the command line tools so you can get a sense of how raw hdl works if there's interest i'll come back to istudio later in the series for example here is a risk 5 soft core cpu being used in ice studio this graphical environment might be an easier way for some to visualize and organize larger projects than say pure hardware description language appio is still a relatively new project so expect some changes as it's updated the read the docs page for appio is the best place i have found for information on installing and using it you'll want to follow the installation guide for your particular operating system but i'll show you the process on windows note that you need to have python 3.5 or greater installed on your computer in the user guides section you can see how to use appio to build simulate and upload your design to the board note that each of these commands actually calls one or more tools in the background like yosis and next pnr to start make sure you're using a version of python that's 3.5 or greater go through the process of installing python if it's not already on your system from there we're going to use pip to install appio however note that i'm specifically installing version .6.7 of appio at least at this time the newest version had issues with installing some of the tools so i'm going to be sticking with 0.6.7 as that's known to work on my system in the future current versions may work and you may not run into some bugs but this was noted on the issues page in the github repository for appio that they are currently updating a lot of the things and backend for appio so i recommend sticking with point 6.7 for now opio should now work as a command line tool in your console if you have issues where it's not recognized as being part of a path you might have to add wherever appio is located to your path i ran into this on some flavors of linux but for windows it seems to work out of the box after installing it using pip from there we need to install the tool suite this is things like yosis and icestorm it doesn't come packaged with appio so we need to use appio to install them from there we tell appio to install the various drivers to support talking to our board take a look at your board if it has an ftdi chip you will need to install the specific drivers to work with that ftdi chip if you're using an ice stick like i am it does contain an ftdi chip so we need to do this extra step if you're on windows you'll want to open a command prompt as administrator to install the ftdi drivers we'll need to call appio drivers dash dash ftdi-enable when we run that at least in windows you'll get zadeg to pop up and we have to go through this process manually if you're on another operating system you shouldn't need to do this step in zotig click options and list all devices plug in your fpga dev board click the drop down list and you should see your dev board listed it might say something like lattice if you've used a board like this before it might also be an ftdi chip or something like that you can also view the list before and after plugging it in to find the new addition to the list so i'm going to click my lattice dev board here and opio wants the lib usb k driver to be installed so we'll select that and click replace driver give it a moment to install the specific driver for communicating with the ftdi chip when it's done click close close out of zig and you can close the administrator command prompt now you should be able to say opio system dash dash ls ftdi to list the various ftdi connected parts you should see a lattice ft usb interface cable that means it's connected to our dev board there is an issue i have found specifically with windows if you have another ftdi chip connected in addition to your dev board you will probably run into this lib usb open failed in this example i plugged in my analog discovery 2 which uses something similar to communicate with usb and having both the istick and the analog discovery 2 plugged in caused this error so if you see this that probably means you need to disconnect all of your other ftdi devices except for your particular dev board so when i disconnect my analog discovery 2 i run that command again and sure enough it pops up with my dev board being connected the first thing we want to do is create a folder that houses all of our projects that we're going to be creating for me i'm going to go into my documents folder in my home directory and create a directory called appio we'll go into appio and store our various projects here one of the cool things about appio is that it comes with a bunch of examples we can call opioexamples-l to list out the examples that are available feel free to scroll through these to get an idea of what we can instantiate look at and modify i'm going to be working with the istick examples specifically let's start with leds as that one's pretty simple we can just call the name of that example with opio examples dash d and then istick backslash examples as you can see that creates an istick directory if we go into there you can see that it creates an leds directory inside of istick if we go in there we can see all of the files that were created as part of this example let's go into the file browser and take a look at what was actually made so we created this optio directory we created istick and leds inside of that our main design it's not actually a program is in the leds.v file so let's open that and take a look feel free to look through this this is a basic hello world example all it does is tie all of the leds to high and it just turns them on the other important file is this dot pcf file which is the physical constraints file or maybe pin constraint file as it tells us how things are connected on the actual board or chip itself this isn't really verilog code comments are given by these pound signs or hashtags and then what it does is it gives a label in this case d1 and assigns it to the physical pin number on the chip so on rfpga pin 99 that's physical pin 99 is mapped to d1 and that's the first led on the board and that's how we get these names when we call them in our leds verilog file if we head to the latticesemi.com ice40 page you can zoom down and you're looking for i believe it's documentation we're using the ice 40 hx 1k that is the fpga chip that's on our istick so click that to download this spreadsheet and you'll want to open it in something like excel the istick has the 144 pin tqfp package so these are the physical part numbers labeled 1 through 144. and i mentioned that 99 is connected to that first led so here's pin 99 you can see that it is indeed a pio connected to one of the i o banks and the next thing you want to do is find the istick user manual and if you scroll through this you can usually find something like a schematic here are the leds so d1 that's what the label was that's connected to a net called led 0 and the actual fpga schematic symbol is divided up into a number of these blocks but you can see here pin 99 physical pin 99 is connected to led0 and you can also find this chart user ios and leds so d1 is connected to 99 and so on and it gives you the color of the led so hopefully those two documents can help you figure out how the pins are connected to various things on the dev board and where you can find the physical pin number when you're creating that dot pcf file the other thing worth looking at is the test bench so the first test bench is written in verilog and you can see it here we're actually not going to be using test benches or writing our own for at least a few episodes because we want to get the basics of verilog down before we start writing these however it's always a good idea to create a test bench to simulate your design and see if it works before sending it off to your fpga and especially before deployment the leds underscore tb.v is the verilog test bench that actually runs the test bench the program that reads that in and runs simulation is gtk wave this is a save state so that when we load up gtk wave it reads this in and it runs the simulation right away basically the other thing you'll notice is this apo.ini initialization file if we look in here it just says hey the board that's supported for this project is the istick we can actually create this file by using appio what i'm going to do here is delete it and then go back to my console and we can say opio boards dash dash list and you can see the list of supported boards at least for this particular version and we want the istick so i'm going to do opio init dash dash board and say i stick all that does is recreate that appio.ini file so if you're creating a project from scratch you'll probably want to do this so that it tells appio that you're working with the istick you can tell the syntax is a little different but either should work now that we have all of the components for our project together the first thing i recommend doing is calling appioverify this performs a verification step using this iverlog tool and this just kinda says hey the syntax looks good we think you can synthesize this and you're ready to go from there you'll probably want to simulate this is always a good idea before actually sending out the project or design to the actual board in this case the simulation step opens up gtk wave it loads in that test bench verilog code and it also loads in that dot gtkw save state so that gtk wave opens up with certain signals here and toggles them in a certain pattern but for now we're just looking at the output leds and they should just be always on when you're happy with the way this looks close out of gtk wave and we want to say opio build this calls yosis to perform the synthesis step for our verilog code and then it calls next pnr to do placing and routing this is where that pins configuration file or the physical constraints file is read in and it figures out how to route the individual connections and set the cells in the chip itself which is the ice40hx1k because the verilog code was agnostic to a particular chip but placing and routing then takes that agnostic design and creates some output that is unique to this particular chip ice pack then takes that ascii file and packages it up into a binary file that can be read by the chip itself assuming we get a success here we can call appio upload make sure your board is plugged in and on this will call iceprog that will take the binary file and send it over to the flash memory of your board assuming the upload process worked all of the leds on the board should be on i highly recommend going back to the lattice page where we downloaded the pin out document clicking on datasheet and finding the datasheet for the ice40hx part so we're going to download that and open it up scroll through here and i recommend using this as a reference and you're going to find this diagram which kind of shows the internal working of the actual fpga these plb or programmable logic blocks contain a number of cells and in fact on the next page you can see that each block contains eight logic cells these are the cells we looked at in the first episode and we're going to be looking at the individual parts of a cell in future episodes and breaking it down as we learn about things like lookup tables and combinatorial logic as well as the d flip flops and how these can be combined to create your digital logic but for this overall view note that these blocks can be connected to one another we have access to some ram there's also i o banks and these i o banks have a little bit of their own logic you can think of many of the pins as being similar to what you would find on a microcontroller and you can configure them to be a input pin an output pin you can sometimes configure pull ups or pull down resistors that are inside of these i o banks and connected to each pin or groupings of pins this particular part also has some dedicated spy logic there's also a phased lock loop that will provide us with clock signals and we're going to explore those in a future episode you also have this non-volatile configuration memory note and this is very important this particular memory on this part is a one-time write only so if you are satisfied with your design and you don't want to change it any longer and you're ready for deployment you can burn it to this little amount of memory here but once you do that's it that part is burned and ready to go otherwise there's configuration logic that will read from an externally connected flash chip from spy usually and that's what gets read in and configures the chip and that sets the cells to behave in certain ways makes connection between cells and among the blocks to create your design on the actual component itself on the fpga you can read in that configuration any number of times but that's why you'll often see external spy flash chips accompanying fpga components on boards and indeed our istick has an external flash chip on it so that when we send our program that binary file using opio upload that gets loaded into the spy flash chip every time you restart or disconnect power from this fpga it loses all of the memory and all of the configuration so each time you boot it up it has to re-read it in from that flash chip and then reconfigure everything which is why it will take a few moments before the fpga starts doing anything when you give it power your challenge for this lesson is to modify the leds.v example so that one of the leds is off you can see here that i've turned off the green led your solution might be a little different but i'll make sure that a link to my solution is in the description if you'd like to compare answers at this point we're ready to start creating our own fpga projects in the next episode i'll show you how to make combinations of logic gates in verilog happy hacking [Music] you

Channel: Digi-Key

Views: 21,772

Keywords: fpga, lattice, ice40, yosys, apio, project icestorm, electronics, digital logic

Id: gtkQ84Euyww

Length: 18min 50sec (1130 seconds)

Published: Mon Nov 15 2021