In system debugging in Vivado using ILA Core and VIO on hardware..

will discuss how to use vivado ila that means integrated logic analyzer and obi or hardware first of all we will see what is illegible the customizable integrated logic analyzer which means ila ip code is a logic analyzer that can be used to monitor the internal signals of a design because the ie4 is synchronous to the design being wanted all design clock constraints that are applied to your design are also applied to the components of the idle code so if you like my tutorials please do like share and subscribe my channel thank you so let's start our today's project first of all create new project we'll give it a name ila [Music] will uh skip two steps we'll select board as we are using this saturn board we'll select this finish now we will create block design we will give it file sorry understood now we'll create here pulsing system we'll add this now we'll see the clock configuration i'll give it 100 megahertz okay first of all we will add la block this integrated logic analyzer okay we'll add view virtual input output now to see the output uh we add one counter [Music] binary counter now we will add the clocks now we will see the parameters now as i will change this mode type as negative instead of x i then in probe uh in the one i will make it 32 bits and make it okay then in the vio uh input zero i change it to 32 bits and output ports we left it as it is as we are only taking the counter numbers in the input ports okay and in the configuration counter configuration will make it 32 bits control will enable the clock enable so that in terms of clock it will change the counter values [Music] [Music] okay now we'll add all the block proofs and i will now we'll connect this clock enable to this robot and we'll add one slice [Music] through this we can we can output the output the counter we can basically see the outputs of counter uh to the leds so will this counter 31 bits will connect to this here and will change give out the out from let's say four say three down to zero so four bits yeah it is automatically generated four bits with [Music] so we'll make it external so original layout this is the total perfect block diagram now we validate the design now like we can see the variation has been successfully completed now the time has come to uh go to the board uh means we have to arrange the pins where this output will be generated for that first of all we will uh and the synthesis okay we'll go to source then we'll have to generate our products now modules has been generated we will create children everyone has been generating now we will run the implementation okay so okay now here you can see the implementation successfully completed now we'll open the limited design where we'll add the pins for led now here you can see that pins are there so here it is showing default lbc modes we'll have to make them and the same mouse 3.3 volt then the output ports so we'll put by default some something has been implemented there but we'll change according to our board and we can see this is the saturn board this is saturn board yeah rgb leds are there so we'll place these pins by 16 by 17. r14 okay now we save it okay here by filename will be given highly now after setting the led pinions now we'll [Music] go to generation of bit stream we'll click there so it will so here it is showing the clothes design this design is out of date because we have changed the values we close the design and now synthesis of design is okay now we will go to the simulation favorite simulation settings we will select this people in the dialogue this is the highly blocked wrapper we'll apply it and make it okay now we'll click and run behavioral simulation now here we will see there is a pio this is the is so we'll add two wave window now we will see it has been added in the clock now as you can see that our this clock is in hybrid state and the output is zero so we'll make the clock force block we will give it leading below this positive edge one negative which will provide zero and it is fifteen and fifty percent recycle hundred means enough period okay then we'll use the timeline for one second and run it zoom it now we will see the so the values are coming just expand it we'll see data's coming now

Channel: Advanced FPGA & Digital Electronics..

Views: 371

Rating: 5 out of 5

Keywords: VIVADO, TESTBENCH, SIMULATION, ILA, VIOFPGA, ZYNQ, TUTORIAL

Id: JsxMD9HRo2M

Length: 13min 21sec (801 seconds)

Published: Wed May 26 2021