HC33-T2.1: Advanced Packaging, Part 1

welcome to hot chips 33 tutorial 2 advanced packaging there was a lot of interest in the program committee in a deep examination of the latest in in packaging which is really enabling uh breakthrough uh new chips that are becoming possible as we're moving to two and a half d and also really 3d packaging approaches and a whole generation of chips will be built from chiplets and so that's the focus of our uh second tutorial this afternoon we've broken it into multiple sections if we first start with an overview of uh packaging technology providers and for that we've invited intel and tsmc to present us with a with an overview of the technologies that they've developed then we look at chips built from chiplets with two and a half d and 3d integration for that we managed to have speakers from intel and amd providing a look at the latest chips coming out and then we close off with a perspective from an independent consulting firm tech search international who will provide as a perspective of which packaging approaches might make sense for which product categories and so we have an independent perspective trying to pull it all together first up is intel the first presenter is ravi mahajan he's a fellow at intel responsible for assembly and packaging technology pathfinding for future silicon nodes ravi has led pathfinding efforts to define intel's packaging architectures technologies and assembly processes for multiple years now um spanning even in the early days of 90 nanometers all the way down to the latest seven nanometer node um ravi's been with intel for quite some time he joined in 1992 after earning his phd in mechanical engineering not electrical engineering in mechanical engineering because why we knew back then already that chiplets and packaging would become really important 20 years later he has a mechanical engineering degree from lehigh university um most important though is that ravi holds all the original patents for silicon bridges which is really the key foundation for in-depth e-map technologies today please welcome ravi ralph thank you i appreciate the introduction very kind introduction and i'm excited to be here okay i am excited to be in the field of packaging i may not have the precedence to be a packaging engineer but i'm certainly in a great place right now uh what i'll do today is the way we have structured this talk is to make it very tutorial in nature in the beginning and then walk you through pragmatic instantiations of how packaging can be used to build really complex and high performance products before i move forward i should first thank a lot of contributors you know engineering engineering like this happens only when a lot of really good minds get together and come up with ideas and this is a partial list of some of the great minds that have worked in this area i also show you one picture if there's anything you want to carry out of this stock you should carry that we can using packaging technologies do heterogeneous integration in all three dimensions and it gives you tremendous flexibility to build products by intelligent mix and match the talk is broken as i said in two parts what we will do is we will start by describing the package as a compact heterogeneous integration platform i will speak primarily about on package interconnects and how it enables high bandwidth signaling i will briefly speak about power delivery and the complexities of power delivery even more briefly about the complexities of thermal management and then i'll hand over the talk to dr sandeep sane who will be the second presenter and he will talk to you about assembly processes the importance of materials and design in the second half of our presentation we will describe product implementations that use these advanced packaging technologies so you will see how the thought i described here translates into products that offer performance the talk outline is this i will speak about the package as a compact heterogeneous integration platform i will describe how we think about package interconnects and how we enable high bandwidth signaling using packaging interconnects and then power delivery thermal managements and then we will transition to the assembly processes materials and design tools and come back for a quick summary if you look at the package and ask the question why the tremendous interest in heterogeneous integration and if you look at the history of the evolution of packaging you will realize that there has always been interest in the package as a heterogeneous integration platform in recent years people have realized that you can use the package to do many things you can use it to mix and match diverse ip and you don't have to integrate all of it if you can't for whatever reason you can optimize ip on different processes and integrate it on the package you can use the package as a means to escape reticle limits you know you no longer have to be restricted to the size of a reticle on a wafer you can get more silicon on a package and for heterogeneous technologies it is a great platform the other is that over time there has been a need and there will continue to be a need as a if i understand architecture for proximate memory which has high bandwidth and low power to enable performance and then the basic reasons why the package has always been of interest as a heterogeneous integration platform first is yield resiliency you know the new process is if you want to make chips smaller to get better yields you can always integrate on package and by being able to mix and match on the package you can make a time to market sort of you can make products available to the market faster all of these make the package an extremely attractive platform for you to integrate different elements and complement the advantages of homogeneous integration that we have gone used uh to over the years okay so let me illustrate what i mean by this by showing you some really interesting use cases the first use case was presented at the 2020 eri summit by sergey shumarayev in this he showed that you could take an fpga and you could integrate different things on that fpga you could integrate custom asics you could integrate interestingly optical chips and you've seen announcements of this nature in the last few years they allow you to do eo or oe conversions very very close to the fpga and the fpga is connected to the uh to the o tile for instance using a high bandwidth low power interface like aib and then an announcement you saw just a few days ago at intel's architecture day the ponte vecchio which we will get into more detail later the one thing you can carry out of this is the level of integration that is enabled by ponte vecchio or this class of processors is simply unprecedented so this sort of gives you the perspective and now let's dive a little deeper into what does it mean when you say you have to develop a package as a compact heterogeneous integration platforms you need to focus on before i get started let me point out that this is still a limited set of factors and there are lots of publications out there that described in their entirety all the factors that are important what i will focus on are the ones that are highlighted by the red boxes i will spend the most amount of time on ensuring that i communicate how to deliver power efficient high bandwidth i o links on package i'll also speak but not i get into detail outside of the example in the previous slide that we have to make sure the package is also capable of delivering a diversity of off package i o protocols doing signaling right on package is a very important aspect of successful package integration as you start bring bringing diverse ip on the package you will have to worry about how to cool it and i will briefly describe what it takes to cool it i will also very briefly describe what it takes to deliver power to all the different functionality you integrate on a package and then i'll hand it over to sandeep to talk about how we do cost effective high precision and quick turn assembly for the success of the package moving forward as a heterogeneous integration platform we have to make sure that we focus on all aspects of design manufacturing materials and process and reliability and sandeep will give you a brief overview of this the topics we don't cover for time are reliability and functionality but they are covered in a more broader heterogeneous integration roadmap that intel is a part of so now let me dive a level deeper let me talk to power efficient high bandwidth on package links and what it takes to deliver these kind of protocols if you take a step away from what a package does essentially a package takes connections on the die for purposes of this discussion these are bumps on the die these bumps land on pads on the package and then wires route out laterally from the edge of the die now these wires route out laterally not in one layer but in multiple layers so if you want to extract some physical metrics you can extract two metrics that are of importance one is the wiring density how many wires can we connect between two die on a package or how many wires can we deliver that go outside the package and connect in the system if you want more interconnectivity then you have to focus on increasing the wiring density what that means is you can reduce the width of the wire you can reduce the space between the wire and you could reduce the size of the pad on which the bump lands or the v as land in underlying layers ideally if you had a system where you have zero pads you get the best wiring density similarly if you want to get more and more connectivity out of a die to the package you should focus on reducing the density of the pumps okay so let me offer an intel centric view of but before i do that let me just quickly go back to the previous slide and talk to you about two dimensions the two dimensions i spoke about are wiring density lateral number of wires per millimeter of the dye edge on a single layer and the other one is the pump density which is an aerial metric the number of bumps per unit area these two metrics and for some reason even though these are physical metrics they are called io as well so i will interchangeably refer to the two now let me offer you the current state of advanced packaging since i am from intel i'll offer you an intel perspective but you will hear different perspectives from different people and you will notice that there is a common theme the common theme is simple you can get interconnect density in a planar fashion using planar mcps oftentimes referred to as advanced packaging using two and a half t if you put stacks of memory next to the compute and one way of doing it is to use what we call emip or the embedded multi-interconnect bridge the vertical interconnects something that has been of tremendous interest for many many years now intel's instantiation of the 3d integration if you will or that z plane integration is through forwards in this instance i show you where active dye are connected to active time and now that you can connect in a lateral manner and in a vertical manner why not combine the two so you combine the concepts of em and forwards and do both lateral and vertical connectivity the images in the bottom show you that these are ideas that have now proliferated into manufacturing and are available for design designers to make real use of to convert into products of great interest which we will talk to later in this presentation so let's talk about planar interconnects okay i will avoid use of phrases like two d two and half d or two point five t and all that kind of stuff just very very simply look at the question of how many wires can you escape from the edge of the die on a package okay for this we take a metric like the half line pitch which essentially is nothing more than number of wires between two two points such that you can repeat beyond that per unit length if you look at this graph it plots the number of wires you get per millimeter per layer as a function of different technologies at the bottom right you will see the traditional organic packages these are the workhorse of the industry these have been around for a very long time for the last at least 25 years and essentially give you wiring density somewhere in the 50 30 to 50 mm i o per millimeter wires per millimeter of dye edge per layer and these are pretty good when you form interconnects which are uh essentially used uh for uh for uh high bandwidth interconnect and for different components on the die that no don't need the density okay if you want more wires you learn to print your wires better which forms the second class of interconnects which are the high density organic interconnects these are with organic dielectrics they have a certain class of advantages and there is interest in these kind of technologies the third broad class of technologies are the technologies that use silicon back-end wiring now we are approaching the density problem from the other end as in instead of shrinking wires we are actually taking the silicon back and wires and making them thicker and thicker even then when you start at two micron wires and two micron lines you get 500 you get 250 wires per millimeter you can get down to 500 with one micron half a micron you get two thousand you will notice that with silicon where you land the vias without pads you get rid of the pad effect and you use silicon back-end technologies if you look at this you now have a series of technologies which give you a very wide diversity of interconnect density the focus among the packaging community is to make sure while we deliver this interconnect density increase we also deliver power efficient connections for increased bandwidth okay so let me now let me switch over to the third or the second class the 3d interconnects where i focus on increasing the bumps per millimeter square okay the workhorse of the industry today for 3d stacks is to use solder based interconnects solder based interconnects can give you tremendous connectivity and somewhere in the range of about 25 and south of 25 though the exact boundary is not defined you would have to transition from solder to copper copper interconnects and the copper copper interconnects can shrink density quite a bit so again you have a very broad portfolio when i have given this talk previously a few years ago i used to say that somewhere in the 20 25 micron range we will transition from solder to copper but you know technologist as always prove you wrong there is a paper here that shows you can shrink which below 20 microns the transition will not be dominated only by the type of interconnect but it will also be dominated by other factors including uh alignment reliability etc flatness etc so somewhere there will be a transition and that transition is already in force today we can transition from solder to copper and there are very good demonstrations which i think a speaker in this talk in this session will also describe the third type is how do you transition from 2d how do you combine 2d and 3d you can do it what i described as co image where you take multiple top tie tiles on a base style you take multiple stacks of these styles and you connect them to each other using emip you connect them to peripheral components you connect them to peripheral memory you notice that now you have in your hands very very powerful methods by which you can integrate a lot of stuff on a package okay why do this why do all of this and how do you define a packaging roadmap so in this one slide i make the case for three things one is even though we are giving increased connectivity there is a growing demand and a continuous demand for increased network and bandwidth density and speed the graph on the bottom right is pretty educational it says that even though we increase bandwidth we also are seeing that as peak flops grow the bandwidth per flop actually trends to go down and there is a need to pull this curve up so packaging engineers i suspect will be in business for a long time because we will have to continue to offer methods by which bandwidth can be provided on a package i will describe one class of on package bandwidth scaling where the dye are very close together and we are focusing on this class of bandwidth scaling for a very simple reason looking at this graph you come to the conclusion pretty simply that if you provide more and more wires you can essentially develop interconnect which we describe as wide and slow you get higher bandwidth with the use of simple circuits so you have a chance to get to lower power and we focus on designing interconnect so that the signals are not lossy the reach of these are limited but they have a very very viable use case as as you will see in later uh later parts of this and the next talk where we describe architectures that take make use of this so i made a case that you must connect elements on a package and they must have high bandwidth and low power this is the basis of forming a roadmap i here describe to you a roadmap that has been created through a consortia of people in ieee the american society of mechanical engineers semi and industry and academic participants we describe a generation as one where you double the raw bandwidth density as in our focus is on providing the physical interconnect hierarchy if you look at side by side or planar interconnects and look at the high density high bandwidth interconnects available today you can use the hbm instantiation as the first point in time where you can connect different die okay today hbm is done at 55 micron pitch in one particular case when you send signals at 2 gigabits per second you can accomplish this using a i o per millimeter square of 331 and an io per millimeter of 500 by the way this is not not io per millimeter per layer but it is the total i o per millimeter if you double it i show one example and i should point out that this is a non-unique table as you can accomplish bandwidth doubling by changing different parameters so this is one good way of doing things okay if we stick to solder based interconnects where as i said the pitches are limited to north of about 20 microns so we pick 30 microns you can accomplish bandwidth doubling generation over generation with signaling speeds at 8 gigabits per second pretty reasonable and at a pitch of 30 microns okay you will pay some penalty in terms of shoreline area and die area but you can accomplish doubling if you say hbm is the first generation you can reasonably assume that columns one and two or gents one and two are what is real today which means we have a lot of we have a lot of work a lot of runway in developing this bandwidth now suppose we use more aggressive bumpage scaling techniques and we shrink the pitch more aggressively you can still accomplish the same thing with much much higher aerial density of bumps similar speeds so you can get dye area and die edge advantages the point you should take away from this is there is a lot of runway for us to do planar scaling of bandwidth on a package and packaging technologies realistically can hit generation five and more so there's a lot of runway a question i often get asked is what is the duration between generations and i always answer by saying that it is about two to three years or maybe more depending on other factors but you can now start doing the math and i have seen instantiations where very very good engineers have demonstrated what it takes to go past past five generations which means there is more runway here than i show and you can read about this in the hydrogenated integration roadmap if you look at 3d scaling now in 3d our starting point is what used to be the starting point of the wide i o interconnected 40 micron pitch here also i show a way by which you can hit tremendous bandwidth densities you can double generation over generation similar duration between generations and you can end up getting bandwidth doubling for at least five and you know engineers are pretty skilled so you can easily infer that you can go past five generations again the same point packaging has a long way to go so that was interconnects the infrastructure provided to offer bandwidth scaling now let me switch to describing power delivery the role of packaging is while it brings different ip together and creates a compact platform it is also to deliver uh power to each element on that platform and as needed through separate power delivery networks that coexist this increases complexity because you're bringing things together by itself this is a pretty deep field i am going to for time be somewhat superficial in the way i describe it by focusing on one element or one style of instantiation but a lot more can be discussed in this area so the way to think about this in my mind is for purposes of this talk how do we bring different ip on a package connect them to deliver power to all those ips make the power delivery path as efficient or as less parasitic as possible so power is delivered as needed as fast as possible and with the right quality so that we can deliver performance so a brief look at history is always useful to see how things work historically most people in the 1980s up to the early 2000s focused primarily on frequency scaling so the goal was to enable faster and essentially leaky transistors and frequency was the name of the game right so you would scale the threshold voltage you would scale the device dimensions and you lived with increased leakage and active power in the mid 2000s there was a transition away from single core architectures to multi-core architectures this was an effort to look at other performance character characteristics and not just frequency scaling more cores offer you performance and they allow a transition away from focus on single core optimization to multi-core optimization part of this is we wanted for power efficiency to get fine grain power control so we had to offer different voltage rails that could be independently controlled and so you see here now with time and this is a representative graph with time the number of power rails on a product as the number of cores increased also increased steadily and depending on functionality you know in servers you have more core so you have more power rails as i mentioned before we are going to talk about one particular means of delivering power which is fiverr the fully integrated voltage regulator intel introduced it on its fourth generation of the core microprocessors and the idea was that you on die or on package are able to step down 1.8 volts to an array of output voltages by having independent power rails you have control and by having control you can control the power dissipation as in get more and more power efficient devices okay this is an example of how fiber was instantiated this is a physical example of how power was instantiated i think one of the big things we managed to do in this time frame was to utilize existing features on the package the plated through holes or pths and create what we call acis or air core inductors okay this instantiation shows you how power would the vrs are implemented on dye and how the aci are used to deliver power and to control uh the delivery of power okay in the first generation of the fiber that intel introduced we achieved an efficiency of 90 this was at a full weigh out of 1.08 volts and the first generation of the fiber aci the air core inductors had a high quality factor okay at that time we had a large xy footprint and we had a 700 micron thick core we achieved 90 plus percent efficiency at that time frame which is pretty good for power delivery and considering the fact that we were delivering power to multiple voltage rails using the fiber in time as the process has scaled the core area shrinks which means we have to shrink the footprint of the air core inductors in the x and y with the push to thin and light devices we went to thinner and thinner cores here i show one example where we went from 400 micron 700 to 400 400 to 200 200 to 100 microns essentially what we are doing is we are shrinking the volume metrics available for the inductors and as a result of this we end up hurting the air core inductor performance clearly there is a need to do something else the something else is the introduction of magnetic inductor arrays magnetic inductor arrays have better performance and by focusing on material optimization and form factor optimization we have an opportunity to improve performance for instance the 10th generation intel core microprocessors use the number of magnetic inductor arrays mis for different voltage domains the use of these inductor arrays essentially helps us recover the loss of efficiency due to aci area scaling for those of you who are more of the research bent of mind or you know in the advanced development stage there is a message here the message is that improved magnetic materials are going to help us get improved magnetic performance and will be one vector that we will have to all focus on to continue to deliver the kind of performance we need at as low parasitics as possible okay i will now transition to the last topic of my portion of this presentation and this is just as important you know as you start aggregating things together you have to manage cooling you have to make sure you fully understand what needs to be cooled how it needs to be cooled and how to make it cost effective i started my career running a group or the early part of my career i ran a group that used to do thermal management thermals is a very interesting and a very important topic and fully characterizing the behavior of thermals is both technically rewarding as well as very very useful in the packaging industry in a single slide i'm going to try and communicate to you that thermal management is something we ought to pay a lot of attention to and let me try and do this this is a busy slide so let me walk you from the left onwards okay as you take that structure i showed you before where you have uh emip plus four wheelers pulled together you have multiple stacks sitting next to each other you have two or three interesting problems one interesting problem you have is that these stacks by definition will have different heights it is possible to get equal heights roughly but there will be some interesting intrinsic difference in the heights which means if you put a thermal interface material in between the stack and the next level that is used for cooling you will have to manage different heights and thermal management to a large extent boils down to first conduction you conduct the heat from the surface of the dye to the next element it could be a heat spreader it could be the base of a heat sink you do it through the use of thermal interface materials by bringing a lot of things together and by putting high conductivity materials next to the stacks you intrinsically include thermal crosstalk and you have to deal with thermal crosstalk the third thing that is hidden in here is that when you stack multiple devices together you have to pay attention to how they are designed because now your thermal resistance is add up and to the first order we design thinking of these as resistance models so it's important to understand the resistances of the stack i show you two technologies that we've discussed in the last few weeks publicly the favaros omni which sandeep will offer more details on and the faveros direct which uses the copper copper interconnect in all of these we pay exquisite attention to the thermal interface resistance to make sure that the designs are done right and we collaborate with people who design our ip to make sure that we don't by design put hot on hot this graph here talks about it 2d or actually a two die stack which can be placed side by side or with two dice which can be placed side by side or stacked on top of each other and it shows you that if you stack them you do inhibit the thermal capability but by intelligent design you can figure out ways by which you start approaching similar capability of a 2d device how do we do this we pay attention to a lot of things in packaging we pay attention to the die to die thermal resistance and how do we manage and understand the interface resistances we pay a lot of attention to the thermal crosstalk between neighboring dye and how they can be designed so that we have designed something which is capable of handling a high amount of power and capable of managing temperatures on different die it's also important to note that all the dye on a package don't necessarily have the same temperature or power or power density demands which means if you have certain devices that have to be at a lower temperature compared to the next you have to manage the thermal crosstalk between them we also look at very carefully how do we design it so that the power density is under control one of the few things intel has done over the last few decades is get very very good understanding of the different power densities power density maps and through models and calibration figure out what is the impact of these and how temperature must be managed on a surface or in a volume as opposed to at individual average levels okay to reiterate what i said we focus heavily on reducing the resistance between the thermal interfaces in cases like omni and foveros direct we are you know getting into a higher level of detail in understanding interface performances we have over the years developed best-in-class metallic thermal interface materials and we have focused not only on the bulk conductivity of these materials but we have focused on the interface conductivity and the interactions between the dye and the integrated heat spreader as well as the interactions between the dye when they are lateral or vertical and the last and probably the most important part where there has to be a lot of collaboration is in the design of what we call thermally optimized package architectures if by design you design a part such that you don't bring high density spots close to each other or hot spots close to each other or you manage the thermal density and level it out you will get to much superior thermally designed parts and co-design of the silicon and package to improve thermals is a very very significant portion of the work we do in this talk hopefully i have given you a overview of all the factors that affect the design of packages and how we go about making the package a compact heterogeneous integration platform i have spoken mainly about performance and now i'm going to hand it over to my colleague sandeep sane who will talk to you about the assembly processes and he will talk to you about materials and design tools and bring this portion of the talk to a close all right thanks ruby it's my pleasure to be here i'm going to start where we left ravi essentially covered most of the elements that were design centric going over the overall interconnect scaling power delivery thermals but now it comes to is how do you make this real right and so i'm going to touch base on what is how do you assemble these things these complex architectures how do you make it effective cost effective and how can you scale to a real high volume manufacturing setup and so what i'm going to go for next 10 minutes or so before i hand it over to question and answer is really give up provide a high level view of what are the assembly processes and some of the challenges and opportunities in the space so if you look at the assembly and test development to enable this packaging the primary focus of assembly our technology development is to deliver high functionality parts that deliver to the product performance but it is very critical that it delivers at a high yielding and high quality and reliability so if you look at now in this plot what are the high level overview of essentially any assembly technology is a wafer comes out of the fab it is typically sorted then it is diced then you go through assembly process and depending on the type of architecture either you spend a lot of time doing wafer level assembly or you do a standard silicon to package assembly then you go through a final test finish and then it is shipped to the or the odm partners where they assemble those parts onto motherboards and at the platform one of the essential parts uh is what intel is very much focused is to ensure that we create a highlighting environmentally friendly assembly and dust processes one of the key cornerstones of intel assembly technology is to maximize the yield there are two broad you can think about in two broad aspects one is when we specially get into this heterogeneous integration space when we commit the dye the silicon to a package it's good to have a known good die or a known good subsystems so intel over a course of several years we have spent a lot of time in developing what we call advanced node advanced sorting capabilities right there are very unique capabilities we have developed so that when we commit the die to a substrate package substrate it is known good also with our over the years there is a significant understanding we have developed on silicon package interactions and how we can develop that interactions and we can maximize through design material developments and assembly processes that interconnect formations and how do we maximize the overall yield right but we don't stop there we also work with our end customers we have our own lines where we simulate what an end customers would see when we ship the parts to them how they will experience when our parts arrive at their factories what environments they will see we try to simulate our friends so that oems and odms when they receive our parts they also experience a very good healthy yields at their end so essentially we are very laser focused to look at from from silicon fab when it comes out to the all the way to the platform and system level we look at all aspects and we develop technologies that support that now when we go into when we look at some of these heterogeneous packaging technologies i would like to walk through what are the some of the big challenges that we see and also of course these are challenges which allows us to a lot of opportunities here especially people this requires a very interdisciplinary approach where people with various backgrounds various mechanical materials and chemical engineers all needs to come together to really make this happen essential part of heterogeneous packaging is we need to deliver to a product performance so meeting the electrical targets is an essential part right so getting the right materials that behave provide the low loss performance for the high speed signals or the power deliveries that are recovered is an essential part of what a package technology needs to deliver it has to be however balanced with what uh it's or what the material sets are can survive through assembly and test and reliability so if you look at this heterogeneous packages this is essentially a complex composite with a wide range of materials that coexist in this form factor one has to optimize these materials so that it delivers to the product performance but also meets the assembly and reliability requirements right so one has to come up with materials such as under fill molds fluxes that go within the assembly process that deliver to the quality and cleanability type of boundary conditions one has to deliver the thermal interface materials with ravi uh talked about uh so that it gives the best uh bulk conductivity at the lowest interface resistance not only that with more and more heterogeneous integration one has to ensure these assembly process and test processes that are developed they can also integrate and mix and match silicon technologies from different fabs and that has to be seamlessly integrated into these processes that have been developed so essentially that is the real complex co-optimization that is needed to deliver a good stable robust assembly process the other aspect of assembly process is as we scale the interconnect as we scale from a standard c4 type of pitch which is typically has been around 100 microns when we go down below 50 40 or 20 microns this interconnect scaling maintaining yields is a very uh complex problem right one has to manage how the silicon warpage substrate warpage and maintain the coplanarities throughout the system so that it can maintain a good healthy interconnect yields and intel we have developed a fairly good deep understanding of this over several years and we are fairly confident that when these when we continue to scale this roadmap to a fine pitch we can continue to maintain these very healthy assemblies the third aspect is really when we take a look at any architecture when the design comes from a product point of view we take a look at those architectures and we can model this up front so we can do these trade-offs really upfront so that we can optimize the designs such that we can make them successful in the downstream assembly and test processes so there's a lot of effort that goes in to make this products a reality and essentially it means that one has to work not only from design space but work with our equipment materials and products engagement with the right business team business units who are defining these products so that we can co-optimize this for assembly and high volume manufacturing setup one of the most important element of packaging technology is the advanced substrates as you may have heard this is a there is a substantial substrate crunch these days in the industry so it is very essential to develop substrate supply separate capabilities which provide you very high yielding uh substrates so there is a lot of engineering that goes into just managing the substrates and developing the uh capabilities so that we can continue to provide uh these substrates to meet the product requirements just if you look at what is expected of a current substrate especially in this heterogeneous integration type of packaging technologies that we are now embarking upon there are multiple aspects of it one is just looking at the form factor these substrate form factors how they are increasing uh if you look at 10 years back the form factors even in the high data centric pack uh segments were much smaller to compare to where we are today they're becoming much larger and larger so maintaining the yield at the substrate manufacturing facilities is very critical when we look at technologies such as e-mabs where we embed these silicon bridges into a substrate it's very critical that it is precisely embedded plus now these substrates have a demand to have a mixed pitch there is a combination of extremely fine pitch for the die to die interconnects as long as with coexisting with a very loose pitch so managing this pitch heterogeneous pitch on a given substrate is very challenging and also it also is a very good uh opportunities to improve the plating chemistries and the tools that are needed to deliver to the quality uh from of these uh mixed pitch that are demanded by the products managing the uh materials as the speeds increase when we go from 56 gigabits to 112 gigs in future even further managing the speeds uh the low loss materials for the high speed i o coupled with demand for smooth copper and demand for a certain barrier less within the substrate is becoming very critical so there's a lot of work that is going on in the space where one has to optimize how the laminations and surface finish that are allowed on these traces that are breaking out of within the substrate not to undermine there's a lot of assembly processes to maintain the coplanarity of these substrates coming out of our suppliers which drives a lot of planarization techniques so that when they come out of the substrate suppliers and when it comes to assembly houses such as intel's the silicon can be placed on it and then we can deal with the good assembly yields right so really if you look at today's substrate it is a very complex uh activities that are needed and intel realizing the needs for this has now we have a substrate line at intel which we work which we develop and we do a lot of our r d up front on many of these vectors that i have elaborate elaborated and working closely with our substrate suppliers so that we can bring these concepts uh in from research phase to a real manufacturing environment fairly quickly so there's a lot of efforts that goes in again optimizing equipment and materials and how this integration at the substrate can be achieved the next aspect when we say co-optimization it is an it's a good word but there's a lot of behind the scene that really uh goes on these are the real i would call our tools and techniques that we have developed over years that allows us to do co-optimization right these are really analytical tools that we have developed across mechanical thermal and electricals coupled with significant investments in our lab setup that we are able to not only do the simulations of some of these design tradeoffs uh whether it's a mechanical integrity of a package when a silicon is put on a package what happens how does the package behaves during uh during assembly or during test environment or even in the actual use conditions we can simulate all this up front and make appropriate design choices and material choices so we can ensure this product is reliable or it is manufacturable same thing goes when we look at thermals when we look at the silicon floor planning we can model a lot of these upfront and understand how the products would behave where are the hot spots where do we need to offer specific what type of thermal solutions we need to offer or even we can go upstream and say how can we do silicon floor planning up front so that we can get the maximum out of the product these are the elements that we have invested substantially with in our environment in at intel and we work very closely with some of the leading academia and consortia to develop some of these unique tools and metrologies that are needed we validate some of these models upfront so that when we design things we can do these trade-offs before it comes to any manufacturing at the same time when we look at our materials these are the materials are very essential we have a strong development with our material suppliers these are materials that can provide magnetic inductors low loss materials or high performance packaging passives so that we can integrate this into a package and provide a predictable and performance enhancement to the end product that we are developing right so it essentially takes uh all these co-optimization and the analytical tools and techniques that we have developed to really make a complex architectures that we are shown especially in when we embark into this heterogeneous integration where we are taking silicon from different fabs integrating on a technologist such as em or four rows or a combination of event photos to bring it all together so that we can manufacture in a very seamless manner at a high yielding process and also deliver to the reliable reliability that the products demand so i call them really these are the technical pillars at intel that really work behind the scene to bring these concepts into reality right now just to summarize what uh ravi has said and also what i can i went through fairly fast but what we are saying what we are observing that there is today there is a broad and growing consensus uh that heterogeneous integration has become a key enabler right this is a enabling technologies on a product uh that is uh becoming a which is offering a distinguishing features for the products there are many aspects of when we design this on package integration using these advanced packaging architectures one has to be concerned about rba one has to make sure it's power efficiency bandwidth is provided it becomes a key enabler one has to also look at some of the delivering clean power to optimize micro uh microprocessor performance especially when you look at the increasing power rails and overall power levels required uh there are new power delivery challenges that are emerging but there are methodologies and systematic ways that intel is in forefront of solving some of these challenges thermal management is also a continued problem or a challenge i would say but it also provides an opportunity to come up with a new materials for thermal interface materials that can elevate these problems along with some of the core design optimism optimizations that we are doing right and finally when you look at the continuous scaling there are when you want to bring this into reality there are multiple trade-offs and innovations that are needed now that we continue to lead the industry to ensure that the assembly yields and reliability are met for this cong this heterogeneous advanced packaging technologies right with that i would i would just stop here we will take any questions we have another talk at 4 45 i believe where we will showcase some of the advanced packaging technologies and the product implementations of this in our next half thank you uh very good thank you very much sundeep um yeah so we have time for a few questions um about five six minutes of questions and uh uh ravi's joining us uh on stage for that as well uh we have more questions than we can answer in the time so a lot of interest i'm following on slack um jumping right into it um a lot of interest in backside uh power delivery power via um questions are um how does uh the uh how does that affect the the stacking of dice and basically um does it take away uh uh uh uh stacks for for for signal delivery so uh uh rng aren't the power delivery and signaling competing for for for for stacks for vertical stacks it's very easy to ask this question and kind of difficult to answer it but let me point out two things here uh we we know how to optimize a combination of signaling and power delivery we think that by doing power delivery in this manner we will free up space in certain areas and we will have to coexist in silicon and uh in signaling and in power but we we have methods i i uh i we are working through the specifics but we have ways by which we believe we can have backside power delivery coexist with signaling uh it'll require a different kind of design and it will require a different kind of test i believe but we know how to do it is what i can say right now and you will see instantiations of this appear in our products ah very good thank you robbie next question um yes yeah so um can you comment about um uh you know your own technologies like power via and also emip and foveros and third-party design kits so intel foundry strategy how do you get access to the design tools so i can i can answer it and let me start with the second question first most if not all of the technologies that we are offering internally are also as part of foundry services to make sure that this is done right we will work with our customers on an individual basis and help and collaborate on designing this right uh the second part of uh so what what that really means is that if you have an interest in say an email-based design for us based design we will work with you to design your products to fit within a technology envelope and we will work with you in uh in the physical instantiation of these and i can tell you that we have worked with a few people now at different levels of detail to actually start co-designing parts if you will as far as the power vi is concerned that's something for a later instantiation but we fully understand how that technology will be implemented and we are working on co-designing it or co-optimizing it and any more detailed lenses we'll have to take a specific product instantiation but we know how to work these since we see all of the best uh tools in our toolkit to bring together the performance you want and i'll leave it at that rough great thank you ravi another question is um so competing approaches fine pitch routing within substrate instead of embedding silicon uh bridges if you could comment uh do you i can tell you no problem so uh you know if you look at the bridge technology uh we do fine pitch routing only in a very localized fashion and sandeep will talk to it briefly in the next part and then the rest of it is course page routing if you will each of those are optimized for their particular use case now there are cases where you could do finer pitch routing on the package and then combine it with bridges uh we know how to co-optimize both of them uh for taking advantages for instance you know if you have fatter wires if you will and separately spaced you can go longer distances so we are optimizing reach in those cases in case of image or high density bridges we are optimizing for lower reaches but higher bandwidth and lower power and we are making sure that we meet the sort of signal integrity requirements so we have put in design tools that help you do it we have put in design tools that help you lay it out and to study the signaling as well together kind of okay thank you maybe i can add one more uh just when you look at when you look at a local pitch uh where you have a fine space and versus if you have a fine line in space over the entire substrate one has to also look at what are the substrate manufacturing challenges associated with the lines fine pitch across the whole substrate right so the advantage of just doing local fine pitch where you just need it is substantially better what we believe than doing it across the whole substrate and then taking subsequent subsequent challenges in the substrate yields and what not great thank you cindy i have an easy question here on slide 23 what is the product in the top left is it ponte vecchio yeah it's a lot of people interested in ponte vecchio and uh and it was teased that uh noticed it was introduced uh at uh intel architecture day earlier this week uh or last week and um so a lot of interesting actually slide 23. it's like 23 okay let me just get to it oh oh yeah this is a this is a schematic representation of what pontific here looks like and you will see more details about this in the second half of the presentation we will actually show you the layout and some more details about how this is laid out very good um so a more technical question um so a lot of talk about uh vertical connections from dadadai do you see any opportunity for doing lateral sideways connections between dye yes ebim is a way of doing lateral interconnect so yes we we see in fact we see you know our technology mcp portfolio offering lateral as well as vertical and combining the two and you will see it again in ponte vacuum where we show how we are doing connections between dice tracks which are vertical as well as lateral high bandwidth density interconnects yeah i think the the question uh was released looking at uh can i take two dye and and run wires right against on the small edge of the dye by sort of lateral abutment uh connectivity no the answer i really think is that's what email yes that's where it even comes in yeah so i would say we leave it here um um ravi and sandeep will be available in slack not right away they still have to join slack but they will jump in all the questions there's a lot more good questions in here and as as we already announced sandeep will be back in in about an hour um to to go into more details in terms of how intel products are using making use of these packaging technologies thank you sandeep thank you thank you ravi thank you next we take a look at packaging technologies from tsmc and to give us this overview i'm excited to introduce doug you he's vice president of tsmc r d and he's also tsmc distinguished fellow responsible for pathfinding of system integration technologies he was in charge of on-chip interconnects um copper low-k c and copper elk as well as wafer level system is in systems integration technologies development including cowas info and so soi ctm doug also was responsible proposing a changed business model where the packaging technologies actually provided also by by buddy foundry prior to tsmc doug worked at at t bell labs he holds a phd degree in materials engineering from georgia tech he's also an ieee fellow for his work on interconnect on ic interconnect technologies closer to home he was awarded the president's science prize which is the highest scientific award in taiwan and quite outstanding or quite stunning doug has been granted over 1 250 u.s patents and has authored over 150 technical publications with that doug please uh give us your overview of tsmc's packaging technologies hi everyone i'm dr rdvp and the tsmc distinguished fellow thank you for attending this tutorial before i get started i hope you and your families are keeping safe and healthy in the face of this global pandemic in this session i'm going to report to you than c packaging technologies for chipless and 3d this is the online of my presentation i'm going to start with a brief introduction of gsmc packaging technology 3d fabric and the new industry transition then i'm going to talk to discuss the new development including the packaging system scaled up and the interconnect scale down later i'm going to move to the new heterogeneous integrations which leverage our 3d fabry technology to provide advanced thermal solutions and also to integrate new components such as silicon photonics and then i'm going to do a summary this is a brief introduction of tsmc system integration technologies we have the new name for the platform 3d fabric it aims to provide cost effective good performance power form factor also show time to market with flexibility and scalability the 3d fabric has two parts one is front and 3d the other one is backhand 3d the front and 3d m2 integrated to partition the chips of soc to help to sustain muscle and the other part is to provide heterogeneous integration capability to integrate the soc and dissimilar chips afterwards this soic can be further integrated with info or call was to provide the whole integration solution there are several versions of technology structures for each technology groups for example cow which stands for chip on wafer stacking and the wafer on wave wafer wow stacking structures for soic and also for chip first which is info integration info r stands for rdl in the connect whereas info l which adds lsi to the audio interconnect to enhance the bandwidth of the interconnect and same thing for koas which is for cheap lost certainly we don't do this to confuse you each version of technology can be more suitable for some applications we want to do good optimization between main core technology and customized solution to meet our customers wide application needs since we started working on our advanced foundry packaging technologies for many years we grow and enrich our fat 3d fabric technology platform to drive new applications such as ai 3g hpc and autonomous driving etc we see a new transition for semiconductor industry from cmos to ccs cc stands for complementary systems for soc and chiplet integration this not only because of many energy analogies between the two we can also leverage sog technologies and infrastructures when working on ccs in the next session i will update you the 3d fabric technology development result which includes system envelope skilled up and interconnect pitch skill down this slide shows the little addition of packaging structures such as info b and some examples of packaging envelope increase such as info os and the call was s that i'm going to discuss in the following info b b stands for the bottom part of info pub it's a new info family member for smartphone applications it leverages our high volume info pop technology and manufacturing experiences and provides your customer the flexibility to stack dram package on it at their contract manufacturer sites info b's package can be less than 450 micron in thickness and can house a mobile soc chip with size up to 135 millimeter square in a small 14 by 14 info package to meet the most stringent form factor requirement info b will be available in the second half of this year info os update for hpc chip led integration our info os offers a minimum of 2 by 2 micron pitch and up to five layers of rdo with a very fine 130 micron pitch copper pump we started the mass production for info at a at the size of 1.5 times of radical since 2018 and in between we also qualify a 1.7 times vertical version in later part of last year and in this year we're going to provide you a new chiplet skin with two plus 8 chip less and it has a 2.5 vertical size is about 51 by 42 millimeter substrate size 110 millimeter square this will be available this year as you can see in this slide we can grow info os in the envelope fairly quick to enable high performance needed by hpc this again is achieved by leveraging our many years of experience on info development and manufacturing to further drive to ultra high bandwidth chip led integration we add lsi which stands for local silicon interconnect to our info os by leveraging both info and coast technologies this new feature drives aisle pad pitch rdl pitch and the bomb pitch or to new high level this solution is available already in this year since a super high-end systems such as super computers for example's compute like one announced a couple days ago which is like the tip of a pyramid can often drive or increase the market demand for hpc infrastructure and consumers etc toward the end the button of the pyramid here we propose two new technologies for this application they are sois which stands for system on integrated substrate and info sow system on wafer they both again leverage our info process capability and technology maturity to achieve the core achieve the goal info sois leverages info to build advanced rdl layers on top of supporting simple substrate to form a new substrate for high performance actually super high performance application and we can stack free chip components packaged components like info or call us passives and so on so forth those are the known good dyes on the new substrate in info technology enables high density ideal design rule comparing against conventional substrate and also because of the maturity of info technology we can quickly achieve very high yield for very large size substrate for example 91 millimeter square and 1 and 110 millimeter square we can achieve high yield in short period of time high quality copper interconnect built with info technology also gives us important advantages in lower insertion loss as you can see from the attached table it's all is shows 25 to 30 lower insulation loss comparing with conventional substrate over a wide temperature range from 25 to 125 degrees c at 28 gigahertz and also 50 gigahertz respectively sois yet has another advantage over conventional substrate which is the high density routing capability with finer nine pitch which is in general less than 10 micron pitch and the view size to gain more service payers and mitigate signal crosstalk a much smaller mesh hall on power ground plans show significantly better return noise it's not to our surprise that sois has robust reliability we use a 91 millimeter square mechanical tv to evaluate the soi's reliability as you can see in the table we passed package label reliability tests and microstructure sanity check after the reliability tests showing again very good robustness in reliability the second example is the info sow which is a four wafer system integration with longer dice compact size with integrated power module and simple modules we leverage info technology from its maturity high bandwidth density low latency c chip to cheap communication and a low pda impedance here is the first heterogeneous integration for compute i o memory passive etc chipless this slice shows the benchmark of info so w versus conventional free chip mcm multi-chip module higher bandwidth density comes from superior line density due to the fine pitch idea generated by info in the beta power efficiency with very low pda impedance simplified and low profile structure can be built here we eliminate both substrate or substrate and pcb since this is a super large system utilizing the four wafer size we need to check for good process uniformity in r and c which is shown on the defense on the left side higher quality copper trays against substrate again coming from info process enable lower loss insurgent loss and city significant power savings tested at 28 gigahertz for various trace lenses this slide summarize info system on wafer technology sows superior performance in electrical power saving compact system with similar solution in the power module push the top of the envelope and the tip of the pyramid up high for our industry in the next few slides we like to update you our koa's technology it is it's a general purpose is to integrate soc chipless and memories such as hpms with one decade of production with high yield and premium quality we continue to enrich the interposer features with extended amino this is for hpc application of course this slide shows the rapid progress of coast technology you can see from 2011 five generation technology migration in one day along with in the process size is more than tripled total transit account is 20 times more memory capacity grows eight times we expect this progress continue in the future for every increased hpc demands when packaged envelope continues to increase and with soc scaling the cpi issue cheap package interaction becomes more challenging for free chip mcm for co-ops however citizen composer serves as a stress buffer cpi stress induced is significantly reduced by sixty percent showing cost is much more immune to cpi this slide shows our leading component solution for hpc we qualify 2500 millimeter square size silicon in the poser along with electrical performance enhancers thick metal and embedded deep change capacitor plus 8 hpm 2e to further push hpc along the years we see larger number of hbms of newer versions from multiple suppliers requested by customer to drive hpc system power speed and memory bandwidth this poses challenges with industry longest r d and manufacturing experiences we prove that we can continue to make it happen one interesting thing koas has been categorized as a 2.5 d solution pretty soon with the integration of soic we see another quantum jump in the challenge and benefits just wonder how we name it based on customers input it's very desirable to shorten design cycle time and faster time to market for co-ops so we developed what we called star which means standard architecture to enable this we have seen 100 percent success success rate for star adopters in 2020 we as we will provide more flexible design options and we expect adoption rate will grow four times this year in addition we would like to unify our 2.5 d solutions for high-end hpc applications with coast l to best optimize cycle time your learning system performance and the economics of skill etc what is cause el we leverage info and coax technology and add local silicon bridge as well as other chiplets including passives at flow 1 to connect cheapness on flat floor 2. this structure increase communication bandwidth with lsi and performance overpower with passives at the first floor the solution is expect to be available in 22 20 22 and 23 time frame on the 3d chip stack in front we have been developing chip on wafer on the right hand side and the wafer on wafer technologies shown on the left side to support various applications the first application for both cow and the wow stacking is hpc we are in the process of delivering n7 r7 on n7 cow technology by the end of this year and plan to do m5 on m5 cow next year in addition we are targeting wow technology for logic on dtc's integration for that we have successfully demonstrated good power tube reduction at the system level testing this is the current plan to develop soic to go with soc nodes the first line shows soc development in the delivery schedule same with c for soic cow starts delivery this year for n7 and 6 first hopefully soic schedule will gradually align with soc in cow scheme and hopefully for ww as well for wow current schedule is somewhat behind cow on sric design rule we plan to scale soic bound pitch 70 node to node enabling bunk density doubling again print node that way we can achieve 2x bandwidth density scaling pronoun and the eep energy efficient performance pronoun migration for more than one decade in the future soic cadency is also planned for two years per his rising note in short term however our soic pump pitch scary may somewhat accelerate this is because of two resist two reasons first the node to node design rule was meant to match with soc node that means nine micron ph for n7 and six and a six micron ph for m5 m4 etc however their schedule is not aligned yet meeting customer request to an iso ic schedule with soc note an soc node is a head as shown in previous slide and the second reason was that our process is fairly scalable we have shown the feasibility of submacron ph bounding so the schedule for the first few soic nodes may be squeezed a bit this slide shows our preliminary study of our submacron soic bound pitch stacking result the boundary interface is shown here good bounding interface with promising reliability is obtained this submicron pitch soic bounding has big implications in the future it can enable direct integration of soic bound and soc beol in the connect it has a long-term deep chip partition implication although soic is considered a front-end process we expect a trend to grow its envelope just like the backend packaging cases big iso ic can be integrated with either more or larger units in 2d direction or more layers in 3d in the third dimension to integrate more memory capacity and all hive functions however summer war has to be addressed to remove the heat accumulated in the 3d stacking next we will discuss some of the new applications provided by leveraging 3d fabric platform to enable innovative solutions to address new challenges such as summer war solution and the situation for tonight's integration this slide shows conventional thermal solution migration paths it can enable good thermal resistance reduction as shown here this is done by pushing for lure in the beta tim which stands for thermal interface material from geotype tin to film type and eventually to liquid metal team however 3d stacking is significantly more demanding in summer solution than ever before we need to continue to explore new and better solution this slide discuss the new thermal solutions we proposed that leverages our 3d fabric technology to further drive some of resistance lower we first show illustration of conventional approach at our upper left corner with liquid metal team located between silicon tdv that stands for silicon thermal test vehicle in fact that means that is soc and copper lead we then evaluate three new schemes first we replace copper need with silicon lead that has preformed microstructures such as trench or pillar to allow liquid coolant to be to approach closer to the heat source at the bottom to remove heat more efficiently effectively as well we also study the new oxide bonding to replace the liquid metal tin to further reduce thermal resistance and we even evaluate the case that we eliminate the bounded silicon need and put silicon micro cooler located at the back of the soc allowing liquid coolant approach even closer to the heat source to hopefully better remove the heat efficiently and effectively here again we want to temporarily name this solution silicon need liquid metal bound to soc this is a skin a oxide team is skin b and when both oxide team and acidic need is removed for this direct water cooling case this is skin c this slide summarizes the evaluation result i apologize for the busy chart okay the first two column represents the liquid metal tin case and the next two columns shows oxide tim case the last two columns represent direct water cooling case for each skin we have two um water a liquid flowing rate we can just focus on one of them take two liter per minute flow rate as an example we compare we compare the nucleometal team versus oxidine versus direct motor cooling case the tin itself shows four you know this is uh okay i don't i didn't include the unit so this is the total resistance for for the liquid metal team 1.5 for the oxide tin and it's zero because for the red water cooling because the um the teens totally eliminated so we end up of the total thermal resent resistance showing from 31 all the way down to 22 for the case of direct water cooling showing big improvements here is a summary of our integrated silicon micro coolant study 3d chip stacking require more aggressive thermal solution oxide team by leveraging our soic fusion bound can greatly reduce the best known liquid metal tin its resistance reduced by more than 50 percent further improvement can be achieved by direct water cooling in a kilowatt power label heat dissipation solution can be achieved by the two proposals oxide team and the dwc system mechanical integrity need further study now let's move to my last topic the integration of silicon photonics the explosive growth of internet traffic has driven data centers to turn to sci-fi for its high speed and no power consumption and we propose a new coupe stands for compact universal photonic engine by leveraging our 3d fabry technology we propose coupe to address the need for wide range of silicon for thomas integration applications to address performance power and volume cost challenges this slide is a quick illustration of the evolution of citizen photographs package migration from packable to onboard optics to cpo core packaged optics drive to the closer proximity between those key components for bandwidth power efficiency and even cost which can be associated with the super large size substrate for cpo case and this is the opportunity that we leverage our 3d fabric technology to provide values monolithic integration can achieve good data rate and power efficiency however the technology note disparity between eic and the pic electronic die and the photonic dye is the main economic challenge for it coupe is our solution proposed for the heterogeneous integration of eic and pic to enable close proximity to minimize electrical property and optic coupling noise this slide compares two 3d stacking skins coupe versus micro bump stacked coupe has lower significantly lower parastate acidic at the eic pic electrical interface 80 no capacitance can be achieved in the meantime 51 reduction impedance impedance comparing with micro bomb with tsv and the 92 percent reduction again from with micro bomb associated with while bounding this slide compares two 3d stacking skins one is coupe the other one is conventional 3d stacking with micro bump code shows significantly lower parasitic at the eic pic electrical interface 85 lower capacitance can be achieved against micro bump and for pda impedance coupe enable 51 reduction comparing with microbomb integrate with tsv and the 92 percent reduction from micro bomb integrate with wire bounding this slide compares power consumption of coupe versus macbook pump either with tsp or with wire bounding coupe achieves 40 lower power consumption at the same speed and also reach 170 percent speaking at the same power this slide evaluates the optical interface of a photonic engine light can be coupled with either vertically with grating coupler or horizontally with age coupler gc as a surface coupler requires cleanness and integrity of the optical path from grating surface all the way to the fiber core for easy on the other hand care must be taken to prevent the expanded optical mode from overlapping the bulk silicon underneath ssc at tsmc we leverage our 3d fabric technology to innovate coupe photonic engine so that gc and ec can be built with essentially the same structure and the dngc is designed in coupe with optical paths intrinsically sealed with dielectrics all the way to the fiber attachment unit achieving very low insurgent loss of 1.03 db for te and for easy application we avoid optical loss due to being overlapped with underlying silicon achieving insertion loss of approximately 0.6 db for both te and the tm modes at 1310 nanometer wavelengths here is the summary tsmc 3d fabric technology platform continues to drive packaging envelope scale up in 3d intercombat density scale down to drive energy efficient performance thermal war could also be addressed for more demanding 3d stacking by new microcooling system ismc and dwc leverage 3d fabric to indiv to integrate innovative coupe for silicon photonics component integration to further enhance this system performance and function for hpc i would like to express my sincere appreciations to it to tsmc colleagues in the following organizations for their strong support collaboration with supply chain public partners are also acknowledged and thank you for your attention thank you very much doug really great uh overview a lot of technology uh quite quite fascinating um we are going to go over the questions i'm going to be looking at the slack channels and picking the highest voted questions starting with the first question over here and that is can you compare how info sow compares with the wafer scale approach that sarah brus is using um uh um okay foreign is um [Music] you did very well yes thank you that was a really good detailed comparison and uh of the two approaches um jumping to a different set of questions um on slide 12 there's a comment or a link to a a post from i think is teslarati and so the audience wants to know does that confirm that tesla's last week announced dojo ai chip is is built with tsmc packaging technologies um that's understood thank you yeah no no problem um and so can you um uh relate to that it says on slide 20 um that uh you can go up to 7000 watts heat dissipation so the thermal solution can bring out 7000 watts how is that achieved and and because this enables designers a whole new headroom in terms of thermal density that they can target from a tdb point of view so can you explain how you can get this much heat out of a chip uh [Music] um [Music] very good thank you and the related question also is um your slide says um slide 36 in particular showing that you can use this uh a water flow rate of two liters per minute uh which is uh 5.8 liters so um yeah sorry getting myself confused um yeah 5.8 liters per minute um yet uh in modern pcs uh the water cooling pumps uh run up to 25 liters per minute so um with with further increased flow rates could you possibly get out even more heat from the system um okay very good thing thank you doug um jumping to some more questions on info sow um can you comment how many dyes have been heterogeneously integrated using info srw so how far how many chiplets how far do you see this technology scaling [Music] um [Music] um [Music] um okay very good thank you and a question related to memory techno memories um do you plan to integrate hbm using info os and a related question is there plan to integrate dram with info sow so perhaps the first question will it become possible to package integrate hpm stacks using info os [Music] um um um um [Music] [Music] is okay great very good thank you that was a great great answer um there's a question on the uh technology nodes choices and options available it says the die stacking roadmap doesn't seem to allow seven nanometer uh stacked on top of five nanometer is is that really a limit and also why does the base die have to be five nanometer with the the die stack on top of it being three nanometers so if you could just comment about uh what limits what what limitations they really are now [Music] okay great thank you doug and uh i'll ask one last question before we go into a break and that's a bit more an open question that is which of these packaging technologies that you presented are you most excited for [Music] [Music] okay [Music] um [Music] yeah it is really nice thank you for that perspective uh doug on behalf of the entire audience here at hot chips um really appreciate you taking the time in your early morning in taiwan for joining us great presentations and thank you for taking the time to answer our questions thank you doug thank you and now we go on break and we resume in just over 10 minutes at 4 45 pm california

Channel: hotchipsvideos

Views: 103

Keywords:

Id: k2CognMJ_9I

Length: 122min 14sec (7334 seconds)

Published: Mon Dec 13 2021