Getting to Link Up with PCI Express in UltraScale+

welcome to a Xilinx quick tech video my name is Jason Lally Technical Marketing Manager with Xilinx in the video today we're going to look at some debug capabilities available to help get a piece Express link up and running the peace Express protocol makes it so that every time two PCI Express devices are connected they negotiate how many lanes are enabled called the link width as well as how fast the link operates called the link speed sign links devices operate from gin 1 which is 2.5 Gigot ran Spurs per second with a link with the by 1 all the way up to gin 3 which is 8 Giga transfers per second with an industry-leading width of by 16 because link negotiation is the first thing that has to happen before we can move actual data across the link and the fact that that are often chips from multiple vendors involved having a simple and easy way to assess what is happening at the link level can save days or even weeks of debug time starting with our ultra scale + family of devices Xilinx has added multiple link debug features to our PCI Express IP to make the link debugging easier and faster than ever before we'll start by looking at our JTAG debugger which lets you visually see different link training state machines including the LTS sm state machine next we'll look at the in system eye scan which lets you look at ayodhya grams while PCI Express traffic is running through the transceiver finally we'll explore 2 gen 3 descrambler blocks letting us look at unscrambled data passing between the PCIe block and the transceivers in both simulation as well as hardware we'll look at all three of these debug features running on our VCU 1:18 board allowing us to run our PCIe link at up to Gen 3 by 16 let's go ahead and get started now we already have our V Vado project open targeting the VCU 1:18 board we'll go ahead and open the IP catalog and search for the PCI Express IP that we want to open in this case we're gonna do the DMA Bridge subsystem for PCI Express now once that opens we'll have our GUI to set up different options we'll select select the location for the PCIe reset and select a link width of by 16 for this particular board on the board tab we'll also change our mode to advance so we can see the tabs that we need to have and we will need to select the link speed to be a Giga transfers per second or Gen 3 now here's the three debug options that we're going to look at note that in order when Gen 3 is enabled s only time that you'll see the descrambler mode to be picked okay we go ahead and get our xci file we'll go ahead and right-click on it and select that we want to open the IP example design we'll select the location of where we want that example design to be and once we do that when we say ok we'll go ahead and it will generate the Bovada will generate a new lavato project with the piece express IP as we've configured it with our example design now when we open the design up you'll see that there are two free running clocks these free running clocks are needed for us to implement our eye scan and will only show up if I scan has been enabled let's go ahead and add a constraints file and now what we're going to do is add the descrambler blocks to our debug setup so that we'll be able to capture those in chip scope so we'll create our new debug xdc file we'll set it so that it's not incentive is we don't need it there and we'll set it as the target once we've done that we can go ahead and run our synthesis once that synthesis design completes we'll go ahead and open it up and what go ahead and do setup debug now there's going to be some extra signals in here that we don't need and you'll see these in the debug wrapper that debug wrapper is for our jtag debug mode which does read those state machines we could look at that and trigger on that if we wanted to we don't need it in our case we'll go ahead and delete that and have only the described signals now here we can add some different ila core settings we're going to leave those as the default and we'll go ahead and say finish that we'll go ahead and set up our debug and once our debug is completed we'll go ahead and close the synthesize design when asked us to save we'll say yes that will store all of our constraints to our debug xdc file so now if we go and look at that debug xdc we should see that all those constraints are there to add our descrambler logic to our chips go module all right now we'll go ahead and run implementation on this design and what's its complete we can go ahead and open it up real fast and we can zoom in will see our PCE block there is the big red block and then our transceivers are up the right-hand side we see the timing has been met we can go ahead and close this and now we're ready to generate a configuration bitstream so we'll go ahead and generate that bit stream and we'll speed that up and let it run once that bit stream is completed we'll open the hardware manager we already have a VCU 1:18 device connected to our design I'm sorry to our PC we'll go ahead and auto connect to it and now we can go ahead and program it with our bit stream now in this case we have that VCU 1:18 plugged into a PCIe expressed a slot and two in a server and once we have turned it that server on we will see that we're getting packets that are coming across and we're able to capture different things all right so the first thing we want to do is we need to for our JTAG debugger we need to go into this minute location and we need to source a tickle file that tickle file is going to go and read the information from our JTAG debugger and store it in a bunch of text files we have those text file now we need to jump outside and we actually have to have tickle standalone tickle install for this and so we go into that same memo net files directory and we can run our reset state machine now here we see that all of the reset states should have been hit which is a good sign that's what we want to see if for some reason we got stuck in one of these states you would not see them all be green and that would give you a hint that there's some kind of issue with reset next we'll look at rx detect TX detect rx in this case we're plugged into a by 16 slot so we see only 8 of those locations are available and here we see our LTS SM state machine so the orange is where in the L 0 state which is where we want to be the green tells us where we have been as well as how many times we've transitioned on each of those paths so that really quickly gives us a good idea of what's going on with our link and if we've linked trained now let's take a look at the in system I scan here we're going to go ahead and add a scan and in this case we are going to select link or sorry lane 16 or lane 15 in this case but the 16th lane 0 to 15 and we go ahead and select ok and that's go ahead and create a scan and oh it's all red well never know if you remember that makes sense we plugged into it by 8:00 slot and so the sixteenth Lane is not receiving any data so let's go ahead and add Lane zero and see what we get and we do that and now we do get an eye that we can discern and see in the middle and we don't have red there so that's good now we can do things where we can make that eye scan more precise and there's ways to do that and you can go look at some I scan quick take videos that show you how to do that last thing we want to show you is these descrambler so we're looking at both the receive and the transmit and we'll go ahead and do a trigger now in a lot of cases you'll want to set your trigger to look for something specific but here you can see that we have a bunch of our pipe interface signals that are going on and it's easy for us to go and we can cap to go in and look at those in this case we have a bunch of idle symbols but this lets us if we're looking for something specific we can set a trigger and then make sure that either we're receiving data from the transceivers correctly or sending it out correctly so that concludes this quick tech video we hope that you'll be able to get to link up with your PCI Express designs thank you very much

Channel: XilinxInc

Views: 3,447

Rating: 5 out of 5

Keywords: PCI Express, PCIe, PCIe DMA Subsystem, XDMA, VCU118, Gen3, x16, debug, In System IBERT, JTAG Debugger, Gen3 Descrambler

Id: CjcqOTDtPPY

Length: 9min 27sec (567 seconds)

Published: Tue Nov 07 2017