[009] DSLogic Logic Analyzer Review and Teardown

[Music] hi and welcome to the open tech lab in today's video we're going to be having a look at the DS logic logic analyzer by dream source lab it's a USB logic analyzer priced at $99 which is a really great price it's a 16 channel logic analyzer with 32 megabytes of internal memory and it can sample at up to 400 mega samples per second which is pretty good specs now the DF logic was originally launched in a Kickstarter by three guys based in China and their Kickstarter was successful they got more than $100,000 in pledges and I have here the second generation of their product this is the dias logic plus now I've done a previous video about sig ROC and logic analyzers which you should check out if you'd like to know more and after doing that video a couple of people asked me about this device but the fact of the matter is I only recently got my hands on one of these and there is a reason for that and the reason is because there's a little bit of drama between the dream source lab team and sig Rock which I'll talk about in a moment but before that let's get the package open and have a look at the device and we'll do a teardown and we'll test it out so let's get started okay so let's get the package open and see what we can find inside so on top first of all we have the logic analyzer unit and I'll have a look at this in a bit more detail in just a second and underneath we have a little tray of extras and accessories we have a USB cable which I've already unwrapped and this is interesting it's actually a USB type-c cable so it's got an unusual connector not the normal micro USB on the logic analyzer end of things we've also got a little bundle of test leads here and we'll have a look at these in more detail in just a second and we've also got a couple of little bags of test hooks now these pest hooks are of the cheap Chinese kind and as I mentioned in my previous video about logic analyzers these are pretty useful so probably going to use these with my better Easi hooks which work much better than these cheap Chinese pros do and that's everything that is inside the package so now let's take a look at the logic analyzer unit and as you can see it's pretty simple we've got a brushed aluminium anodized enclosure here and on this end we have the USB type-c connector we've got a status LED and then on this end we've got the connection header which we attach the probes to now the probe connection port consists of this two row PCB header you see here and the pitch of the pins on this is point zero five inch which is half the pitch of the more standard point one inch header that you see everywhere and the way this works is that the bottom row of connection pins is all connected to ground so every single input pin has a corresponding ground pin which is a distinct improvement over the earlier DF logic logic analyzer and then UB might be obviously these little slots that are adjacent to the header and the way it works is that when you come to want to connect probe to this thing you have these little probe groups that are groups of four coaxial leads and these slot into these little groups here and that's how you attach four probes to the logic analyzer so I quite like this arrangement and we'll have a closer look at it in just a moment so now let's do a little teardown and find out what's inside this thing so we've got four screws to remove there we go now there doesn't seem to be much on this side of the PCB so let's remove these four screws and then we'll be able to get the board out now this thing just lifts out just like that there we are now if we have a look at the top side of the board we can get a pretty clear idea of how this board actually works and of course the logic analyzer is a relatively simple thing it just samples the data coming in on these input port pins here and then it packs them into USB package that get sent to the PC through the USB port now it's no surprise to see in the middle of this thing a cypress fx2lp which is a bus adapter that is able to take data on its parallel pins here and pack the data up into USB packets then it can also do the reverse taking data from the PC and playing it out of the parallel pins it's pretty bi-directional depending on the needs of the application and the other function of the FX 2 is it has a built-in 8051 core which is able to supervise the communications between the board and the pc and it's also able to control the functions of the rest of the board and do anything else that needs to be taken care of on here now the muscle of this board is this zhiling spartan 6 FPGA and this is the lx9 model which is the second smallest FPGA of the series and this takes the data that's being sampled here and it's sort through which channels are enabled and it packs the data into data words and stores them in an internal buffer and then it also transfers from that buffer into the FX 2 and through the FX 2 up into the PC now this device runs in USB 2.0 high speed which will give you a transfer rate of about 200 megabits per second which is pretty fast and a lot of the time the data rate will be slow enough so that you can transfer between the samples sample data coming in through the input port and transfer it up to the PC in real time and this is called streaming mode and when you're running in streaming mode there's really no limit on the amount of data that can be transferred you can transfer millions and millions of samples up to the PC up to the limits of whatever the PC can store so it's very very useful you can just have an endless sampling session in that case but the problem is that if you want to sample at higher and higher speeds and you want to have more and more pins enabled it's quite easy to enter a situation where the total transfer rate exceeds that 200 megabits per second ceiling and if that happens there's no way that it's possible to continuously transfer up to the PC anymore and so this chip comes into play in that case this is a 32 megabytes the Urim made by micron and this is used when the device is running in buffered operation and in that case it samples at high speed that it's full speed of 400 megahertz or whatever it may be and it can capture data up until this SDRAM is completely full and then when the SDRAM is full and the sweep is complete then the FPGA will transfer the data out of the memory and through the x2 up to the PC in slow time which can be really useful if you want to capture a really short high-speed burst of data so now I've got the board under a microscope we can have a little look at how the input front end works so you can see here on the right we've got all the input signals on the header here and then the first thing each input encounters is this 7.6 kiloohm pull down to ground and this resistor is present so that when no input is connected to the pin you don't want the input floating around picking up spurious inputs and crosstalk or whatever so this resistor is just there to tie that input down to ground such as always read as a zero in that case and then the signal is connected into this electrostatic discharge device and this is used for F every fourth channel here so it's got four channels connected to it and it basically consists of four sets of clamping diodes and a Zener diode and it's there to protect the device from any high voltage spikes that might come in from static discharge on the input which is very important to protect the fpga from getting damaged by that kind of spurious signal coming in and then in terms of just normal excess voltage on the input from excess amplitude on the input waveform the clamping is done inside the input of the FPGA here and each each input of the FPGA has a pair of built-in clamping diodes between power rails and this just protects the FPGA from excess voltage on the input but the input clamps within the FPGA can only sink or source so much current which is why there's a 30 ohm resistor here on each channel and this is there to limit the amount of current that can flow into the FPGA or out of the FPGA if we have a voltage come in as to positive or to negative now apart from this the board doesn't have much else on it at all it's just got this little I squared C EEPROM 16 kilobytes of storage to store the firmware for the FX 2 on it and it also has a switch mode power supply and that is about it so by way of comparison here is an image of the front end from the earlier D s logic pro which preceded the D s logic plus and you can see the design is pretty similar we've got the isolation resistor before the FPGA which is off the image on the Left we've got the ESD protection device in the middle we've got pulldown resistor which comes right after the input but the main difference is that rather than just having the pulldown resistor we've got a full RC filter Network here and this is present too I think to try and give the input signal a bit of a helping hand to try and enhance the high frequency component coming in from the device now I am a bit suspicious of this design you do see it in a few different logic analyzers that are on the market but I'm not sure that this is a particularly good idea for one thing you can end up adding a lot of ringing to the signal coming in so that rather than getting one edge you get multiple edges that's created by this circuit just ringing away and also you are then applying a reactive load to the device under test which is not going to be a good thing you that would be quite unexpected to have the logic analyzer doing that to whatever you happen to be probing so on the whole I'm pretty glad that they simplified the input design in the new DES logic class it seems like a better idea to me so yeah very good development in my opinion ok so now I've got the logic analyzer back in one piece and now I want to take a little look at the probing arrangement they've got here now I've spoken about logic analyzer probes in my previous video on logic analyzers but the short story is basically that it is really hard to do a good job of probes on logic analyzers in general now by way of comparison this is a normal oscilloscope probe a times 10 attenuator probe that you'd find on any typical oscilloscope and it's surprising how much engineering actually goes into this thing and the reason for that is that it has quite a lot of unique properties it has very high impedance very low capacitance and very low reflectance in other words if you have a circuit that you're trying to measure a signal off of you don't want the probe to distort the signal by loading it up in various ways or reflecting the the signal in funny ways and so in electrical terms it's as if this thing is light as a feather it is almost invisible to the circuit when you attach to it and to make this happen it's certainly no simple job it's actually quite complicated the various analog trickery that goes on inside this thing but the problem with this is that when you want to build a probe like this it's okay for an oscilloscope which might have two channels or or four channels but when it comes to building a logic analyzer you might have eight channels or sixteen channels and it will become impractical to build a proper attenuator probe on each channel especially for these cheap USB based logic analyzers now most logic analyzers you encounter don't do anything in the way of quality probing at all so most logic analyzers just have a load of flying leads and so each channel is just a flying lead and the problem with this as I mentioned previously is that each of these flying leads is like an inductor that you're attaching to the circuit and so by attaching that inductance you're attaching a reactive load which is going to do strange things to the signal you're trying to receive it's going to apply various distortions now if we look at the DF logic we can so they've tried to do something rather interesting so each of the signals here rather than being a piece of flying lead each of these probe wires is actually a really thin bit of coaxial cable and then at the end there's tiny little pieces just a couple of centimeters a flying lead and then you can attach some test hooks on the end if you want to do that now the benefits of doing this is that it really will hopefully massively reduce the inductance of the lead itself because if you look at the size of the inductive loop here it's absolutely tiny really really small when you compared to a traditional arrangement in a traditional logic analyzer in this case you're going to have your probe wire you can see the green wire and you're going to be probing something on your board and current must flow all the way up the green wire into the device and then all the way back down the ground wire and there's only one back down to the board and so we have an absolutely enormous inductive loop as a result so we're going to be applying a really large inductive load on the board and the DES logic doesn't have this and the benefit this is that the loading characteristic of the probe should be much much more consistent at different frequencies so with an inductor the loading characteristic that it will apply to your your device and test will vary as you get to higher and higher frequencies whereas this thing mostly the loading will happen from the characteristic impedance of the coaxial cable and therefore the loading characteristics should be much flatter across the frequency range which is really really good I think this is probably a much better way of doing things but there are a couple of downsides to doing this and to explain those we need to have a little bit of a closer look at how these coaxial transmission lines actually work so here I have a schematic of a typical coaxial transmission line setup and as you can see on the Left we have a AC voltage source and this is a stand-in for whatever kind of data transmitter we might have in this circuit and then on the other end we can imagine that there will be a either of some kind I haven't drawn it but it would go in here somewhere now it's very important with transmission lines to make sure the source and the sink are properly terminated which is why these two resistors are here and without them you get awful problems with reflections as the signal bounces up and down the transmission line being superimposed upon the signal that you're trying to convey from one end to the other and it makes a real mess so it's very important to make sure that each end is properly terminated with characteristic impedance now in electrical terms the transmission line is equivalent to a distributed inductor and capacitor it's an inductor because this wire going down the middle has a certain inductance along its length you can think of it as a piece of a coil just floating around inside this this cable here and it has certain inductance as it goes along and as a distributed capacitance because the central conductor and the the outer shield they act as two plates of a traditional capacitor so there's certain capacitance between these two conductors which are offset from each other so in that way it's both an inductor and a capacitor at the same time now to help think about that it's sometimes helpful to think of it as just an infinite ladder of inductors and capacitors tiny little inductances and capacitances spread along the length now to a DC signal this just looks like an open circuit so no current will flow from the conductor in the middle to the shield but to an AC signal such as binary data that we're transmitting this will look just like a resistive load and it turns out that no matter how long the cable is all of these inductors and capacitors add up to a certain impedance this is called the characteristic impedance and in most coaxial cables this is designed to be 50 ohms and no matter what the frequency is it will experience roughly the same 50 ohms of loading and this is the case in with the coaxial cable in the BS logic it has that 50 ohm characteristic impedance just like most coax does therefore when you attach the logic analyzer to your device you need to be aware that you're attaching a 50 ohm load it which will reduce the amplitude of the signal on the board and it will increase the load on the transmitter on the board whatever that might be so that's something to be careful of and there is a second problem if we turn back to our schematic as I mentioned you can see there's both the source and sink termination resistors and these have to be present because otherwise they'll be reflections that either enter the transmission line but the DF logic probe doesn't have either of these now it's not really possible to add a source termination to the logic analyzer probes without building something much more complex like an oscilloscope would have and they haven't added any sync termination resistors inside the device itself I guess they wanted the logic analyzer to be a high impedance device which is no surprise it will be quite unusual for it to be a low impedance logic analyzer but all the same it doesn't have the correct termination that needs to go with the transmission line here and therefore there are going to be some reflections which could potentially impact the circuit we're testing now to help demonstrate the effect I've got a little simulation so let's have a quick look at that so I've got a rough simulation of the probing setup running here in circuit jf and 30 GS is a completely free circuit simulator it's web-based and I'll provide a link to this simulation in the show notes now if you watch my previous video on logic analyzers you would have seen my simulation where I showed how the flying leads can attach a certain loading to the device under test and so I've modified the simulation a bit to try and roughly represent how the DF logic will affect the device under test so in this schematic we have the device that we're actually attaching to along the bottom here and on this device we have an imaginary data source represented by this 50 megahertz square wave generator and it's transmitting something down a transmission line across a PCB to some kind of receiver maybe another chip on the board and transmission line is correctly terminated at both ends and then we have a little break in the middle to represent the point that we've attached our logic analyzer now with this logic analyzer I've tried to put in some representative values for the internal characteristics from the things we know about it and then of course we have our coaxial transmission line here and then we have a twenty little bit of inductance just to represent the little bit of flying lead out of the probe end now it's quite interesting how this is working out because you can see the issues caused by that lack of termination you might be able to see that we have quite a lot of reflection going on inside this this coaxial cable here now on the Left oscilloscope we can see the voltage received at the receiver over here and on the right we can see the voltage received inside the logic analyzer now the signal is looking pretty mashed up in both of those oscilloscope traces it's not the worst thing in the world in logic analyzer hopefully we should be able to extract a reasonable square wave out in the logic analyzer but it's looking pretty glitchy and nasty inside the device on the test so not only have we applied a 50 ohm load to this signal but we're attached to here which will reduce its amplitude but we're also adding a whole load of reflections which appear as these glitch pulses that are superimposed upon the signal we're capturing here and that this is could be quite a problem because these these edges could be interpreted by the receiver as like a spurious edge which might be interpreted as a extra clock edges and cause all kinds of problems now hopefully in the real world there will be enough parasitic capacitance in this system to soak up these little glitch pulses so I wouldn't be convinced that these would ever really manifest in the real world but it just goes to show the kind of effects that you can theoretically get when you try and attach something to a circuit like this now you might be wondering at the end of this whether the DES logics coaxial probes are actually an improvement over the more tradition or flying leads and my sense is that it probably is an improvement for the problems we've seen in the simulation so for one thing we're hopefully going to get a nice consistent frequency response across the frequency range by having this 50 ohm characteristic impedance rather than having two massive inductive loads that we're attaching to the circuit and hopefully with that we are also not going to get too much in the way of phase shifts being attached to the device under test also which should be an improvement but it's a little bit hard to tell I don't have the equipment to definitively tell how well this works out but for one thing we can do is that if this coaxial arrangement is causing a problem we can always take it off the logic analyzer and do our own custom probe set up just by attaching directly to the header so that is always an option if things are not working out with any logic analyzers probes now there's no substitute for a real-world test so I've set up a crude little experiment to find out if things are as bad as they appear in the simulation so in this test I've attached my lattice ice 40 FPGA development board and I've configured the FPGA to put out a 25 megahertz square wave and then I've attached this output signal to the oscilloscope so that we can see the shape of the signal that's being put out by the board and then in addition to attaching the oscilloscope I can attach the logic analyzer and we can compare the shape of the signal with the logic analyzer attached versus what it looks like with no logic analyzer attached okay so here you can see the output from the logic analyzer and as you can see we're getting a nice square looking square wave just a little bit of overshoot here now just for comparison I will save this as a reference signal and that will allow us to compare now let me go ahead and attach the logic analyzer clip it on very good and now let's compare that with the single before you can see that the logic analyzer is damping out the ringing a little bit now the amplitude of the signal hasn't really changed at all and the reason for this is that the FPGA is a very very low impedance signal source so we wouldn't expect to actually to be able to reduce the amplitude very much okay so let's try again at a higher speed so this time I've configured the FPGA to put out a 200 megahertz signal and this is a 200 megahertz oscilloscope which means that the bandwidth of the signal we're putting out the fundamental tone is right up at the limits of the bandwidth of the oscilloscope which is why this signal looks like a sine wave because any of the higher frequency harmonics that would make the signal look more square are being filtered out because they're beyond the oscilloscopes bandwidth and also this time I've set the channel coupling to be AC coupled and by this that this means that the waveform is centered at zero volts between the peaks rather than it being and it's true offset between zero and 3.3 volts and you can see that with no logic analyzer attached we've got an RMS voltage of 1.3 4 volts or so so now let me just save that signal as a reference for comparison there we go and now we're going to go ahead and attach the logic analyzer that's good do that there we are ok so now you can see that with the logic analyzer attached we've loaded the signal a little bit and now the voltage is dropped to 990 millivolts or so so we've got a little bit of a drop in voltage and now for comparison I've hooked up the FPGA with a more traditional oscilloscope with flying leads and as you can see on the oscilloscope trace the results are not pretty so the upper waveform here is the unloaded signal from the FPGA the middle one here is the reference from the DF logic and then at the bottom here in the middle we've got this result when we attach this flying lead based logic analyzer and as you can see the signal has been absolutely destroyed and we've only got RMS voltage of about 300 millivolts now and this would cause major major problems for the functioning of the circuitry in the device under test so on the whole I think the results of this demonstration are pretty impressive in terms of demonstrating that the design of the D s logics probes are really really working so now let's have a little look at the software side of things so I first became aware of the D s logic way back in January 2014 in the early days of their Kickstarter and at the time I was a very active contributor to cig rock and as I mentioned in a previous video I originally the cigarette GUI pulse view and I'm not such an active contributor now but at the time I was doing a lot of work developing the the GUI for cig rock and so when I found out about the DES logic I was really interested in comparing the design that they had implemented with the cig rock pulse for you designed to see if there are any ideas in their UI that would be worth replicating in Sigrid now at the time they were offering a link to a beta release of the DF vu software that was available for Windows only at the time and so I downloaded it and I ran it up in wine and it ran quite nicely and wine which is great and I began playing with it and it seems like a pretty simple logic analyzer you are you can see it here in it this is the demo device and we've got a variety of signals displayed here and over time as I tested it more and more it began to really feel very familiar to me and little by little late I began to notice little things in the UI so that you might not be able to see it but the little Chevron on the timeline it looks very similar to the one in pulse view is not a big detail but it's something I also noticed the way the samples text in this drop-down was written is exactly the same as it is in pulse view and the way demo device is written in the device selector here is exactly the same as it is in Sigrid and then I went into this little dialogue here and the way in which the text enable all and disable all was written again was exactly the same as it's written in cigaratte but apart from that everything else in the UI was different so there isn't that much that would look similar but I began to realize more and more that this may well be a fork of cigarette policy but the conclusive evidence came when we started doing a bit of binary analysis at the DS logic program files and by running DF logic through strings and graphing for sig ROC we found a whole bunch of matches and many of these bits of text are from the official sig ROC source code repository and so there we had the official evidence that they had taken the source code from sig ROC they'd fought their own version now at this point there was a fair amount of consternation from the ziggurats development team because testing the DSP software it had the appearance that they had gone to quite some lengths to remove all references to sig rock from the user interface so here we are in the about screen you can see that big rock isn't mentioned and all the names of the original authors have been removed and the GPL license has been removed it's not mentioned anywhere and overall they'd seem to try and change things as much as possible just so that it wasn't so obvious that their user interface was derived from Sigrid and so there was certainly quite some annoyance that they chosen to do this and so the cigarette guys decided the right thing to do would be to try and encourage them to be in compliance with the GPL and so we collectively wrote an email to the dream source labs team explaining for them their obligations under the GPL license and there was a bit of back and forth between dream source labs team and the cigarette developers but in the end by the end of January they had made an initial release of the source code on github now in many ways this is an interesting case study of how open source projects can end up clashing with Chinese development teams and even for this stage the dream source lab skies are controversial within the cigarette community and there are two main schools of thought about them the first is that they were being deliberately deceptive that they were trying to pass off code that was mostly written by Zig rockers their own and in so doing they were hoping to get some advantage that they will be able to provide this software without having to release the source code and in many ways that's quite convincing and they did make a lot of money off their their Kickstarter and they've never contributed anything back to the parent projects which they depended upon to get started that's one mode of thinking about the dream source ladder team the other is that they were doing some kind of interim thing they weren't planning to release the source code for a beta release they weren't aware that they were required to buy the license and when the cigarette team reached out to them and made clear their obligations under the GPL they were happy to release the code and fulfill the obligations that they had to the license and they continued to update the github repository with new patches and even accept pull requests here and there so I don't think it's ever been conclusively proved which it is so perhaps you'll have to make your own mind up on that one so if we flash forward to the present-day build of DSU you can see it's advanced quite a bit it has this beautiful charcoal gray theme which is quite an advancement on the appearance of the beta version and the early releases of BSU I think this build looks great and in many ways it's quite similar to use to cigarette policy because of course it's derived from it but in quite a few ways they've improved upon pulse view and they've got quite a few features now that are present here but actually are not present in policy so they've moved ahead in some ways now some of you might be wondering whether it will be possible for these features to be integrated back into Sigrid given that this is all open source software and the answer is that in principle yes it would be possible and it would be great if these features could be ported over the only issue is that well for one thing the code quality isn't quite up to what it needs to be to go into siga and by that I mean for the most part they focused on the needs of the DF logic device whereas for patches to go into cig rock they need to be able to support any logic analyzer device and support them properly and so in a way it's easier for the DS logic guys to add features to their GUI because they only have one device to focus on so that's one issue and the other is just that some of the time it can be quite difficult for Chinese development teams to contribute to Western open source projects and of course there's a language barrier and a timezone barrier and there are also various cultural barriers so for example Western open source projects usually run on a system of peer review where patches are criticized and improved until they're ready to go into the project but if anyone is coming from a face-saving culture then that process of critique could be humiliating for the person who's trying to participate and so it can be quite difficult for some guys to feel like they are comfortable to contribute to an open source project and added to which in economic terms sometimes it's just not a priority for the team to focus on trying to get their patches upstream so it's understandable that they haven't contributed the patches back to sig rock but the code is available for people to come in and try and derive things from their work if there are useful improvements that can be brought in that way now let's just have a quick look inside the device options dialog and you can see there's a few things of note here so first of all we've got the operating mode and we can run in buffered mode streaming mode or internal test mode now in streaming mode of course the data is being transmitted straight to the PC over USB and as I mentioned earlier we're going to be limited by the bandwidth of the USB high-speed bus but on the plus side we get an infinite sample depth we're just limited by the amount of memory inside the PC and in this mode we can sample from up to three channels at a maximum of 100 mega samples per second whereas if we switch over to buffered mode we can go faster we can get through three channels at up to 400 mega samples per second which is really really good but then of course we're limited by the amount of storage inside the device although it does have quite a bit of storage so that's not too Greater limitation and then in addition to the bus mode the operating mode we have the threshold level so you can configure the transition voltage between a a high and a low and this means that the logic analyzer is compatible with various families of logic signaling whether it be 3.3 volts or 5 volts or 1.8 volts or whatever it may be you can just set the threshold level so it sits between the voltage of high and low in whatever you happen to be working on we've got filtering so we can filter samples coming in and this one's interesting so the device supports using an external clock signal which is sometimes called a synchronous logic analyzer a synchronous logic analyzer is one where the clock signal is provided by the device on test so for example if you're hooking onto a parallel bus of some kind or you can run it as an asynchronous logic analyzer where the sampling is done based on a clock generated inside the logic analyzer itself which is perhaps the more conventional type but apart from that that's about it for the device options page now the triggering options are quite sophisticated and complete we've got the simple triggers rising edge falling edge any edge high and low and these can be applied to any of the channels here just by selecting them like this and it also has support for advanced triggers so we've got options for multi stage triggering the HP style triggering that you see in other logic analyzers we also have support for serial triggers and I believe you can find various words within the data stream from a single channel and this looks really interesting and powerful now to really talk to the logic analyzer I want to find out how well it performs when it's in the maximum 400 mega samples per second mode and within a synchronous logic analyzer you have to be aware of the Nyquist frequency which is the maximum frequency that you could possibly ever receive that the logic analyzer and that is half the sample frequency and the reason for this is if you put in a square wave at this frequency at 200 megahertz you're going to have one sample which is a 1 and 1 sample which is a zero and it's not possible to make a square wave and capture that with any higher frequency than that limit now with logic analyzers you'll typically need to go even lower in frequency than the Nyquist because for various reasons you usually need to over sump or the square wave that you're capturing so let's have a look at what the results are like when we run that test so we're all set up here I set to capture 64 K samples at 400 mega samples per second and I've set the voltage threshold to 1.5 volts on a 3 volt output signal so let's see what happens when I trigger the capture there we are so on the top row we've got our 200 megahertz square wave being captured and on the bottom row we've got our 100 megahertz the quarter sample frequency here and you can see the 100 mega Hertz seems to have been captured quite nicely we see if we zoom out a continuous waveform here a continuous series of ones and zeros one after the other and you can see in the little blue pop up here that we've got a frequency of 100 mega Hertz now the capture for of the 200 mega Hertz square wave is less good and this is for the reason that I mentioned earlier that you can have problems when you try and capture a Nyquist frequency signal because it is possible when you look in this area the samples are being captured but unfortunately because the waveform coming out of the FPGA isn't quite symmetrical you can be in a situation where the logic analyzer will capture all the samples as zeroes because every time it samples it just happens to coincide with a trough of the signal it's capturing and it never sees any Peaks or vice versa and so you can see that as the the crystal oscillator within the logic analyzer and the crystal oscillator on the FPGA board come in and out of phase with each other you can see we get these little bursts of signal but that wasn't really the point of my test the point was to validate that the logic analyzer has the full 200 megahertz of bandwidth on the input and because you can see that we do from time to time get a valid 200 megahertz signal being captured this demonstrates that the logic analyzer does have enough bandwidth and it is able to capture signals at this frequency now turning to sig ROC cigarette has had support for the D s logic devices his the last major release and that release came out in June this year and he added the very first ever device driver for DF logic devices that Sigma is ever had and since that time I've been working on improving this driver I've added support for the DF logic plus the device were reviewing today and I had to do that because it was part of another project which I'm working on and also that project will be the subject of an upcoming video now at the moment the driver has support for capturing using the streaming mode add up to a hundred megahertz which is what I've got captured here this is just a load of noise this is nothing significant but say you can see the drivers working but many of the more advanced features of the device are not yet enabled inside the driver so for example it doesn't support external clock signal coming in it doesn't support the filtering and some of the more advanced filtering modes and of course the buffered mode of operation isn't yet implemented but this is something that wouldn't take ever so much effort to implement and at the moment I don't have time to do it myself but if someone else is interested in digging into the driver and working on improving it I think this will be a very interesting project to get into if someone's looking to do some work on sigrid now interestingly it's not just the D s view source code that they've released also a various points they've released things like the hardware design files for the FPGA and even the schematics so this is the schematic for the original D F logic pro oh now they haven't been consistent about updating and releasing upgrades and things to all of these files but still they are quite interesting to have a look through even if they are previous versions so if you're interested in having a little bit more of a detailed look about how this logic analyzer works you can have a look at the files and I'll link them in the show notes so at the end of this review its prime for me to give my verdict and I'm feeling pretty positive about this device the price is very very competitive compared to other logic analyzers with similar features $99 is a great price for this device and on the software side of things I would say D SVU is really matured in many ways it's pretty nice to use and if you want to use it with sig ROC that's also an option and I think I will be using it mainly with sig Rock going forward in the future because I think cigarettes a bit more powerful than the SVU in terms of the things it can do for you and on the hardware side really this logic analyzer is just about as powerful as it's possible to be as the USB logic analyzer now it is limited in its streaming speed to the PC by USB 2.0 so it could go up to USB 3.0 SuperSpeed and that would mean it could stream much faster to the PC but there are other problems with that not least the fact that it adds a lot on to the bomb cost and so it will probably add about 30 or 40 dollars onto the sale price USB 3.0 is currently not cheap to add to a device and in terms of the sampling rate 400 megahertz is is pretty good and it would be possible of course to increase the sample rate with upgrades to the design but then issues relating to the probing becoming it become even more significant and probes become more and more difficult and expensive to the design so you don't see many PC based logic analyzers that go hot much higher than that 400 mega samples value and so really this logic analyzer I would say about $99 price point is basically everything you could reasonably expect from a USB logic analyzer so I think this device is pretty cool and I'm actually glad that I've got one it's great now if you're interested in purchasing one of these devices you can get one from dream source lab calm and I'll link that in the show notes now in the bye page there's something a bit weird here because they only have the old generation products listed like the DS Logic Pro and the DF scope and so I'm not quite sure what's going on here because when I ordered the DES majek Pro I got the DS logic plus delivered which is great and I think that's the DF logic plus is the one you probably want to order so I'm not sure what's going on with the website they'd seem like they need to update it a little bit and if you're going to purchase one you're going to want to make sure that your auto gets you a plus rather than the old pro now that just about wraps it up for this review I hope you found it interesting if you did please hit the like button and subscribe and if anyone's interested I'm also running a small patreon if anyone wants to contribute to supply the channel with equipment of whatever so anyone who's thinking of contributing for that I'm very very grateful and for anyone who's watching thank you very much and hopefully I'll see you next time on the open tech lab you

Channel: OpenTechLab

Views: 79,343

Keywords: logic analyzer, dslogic, saleae, logic, usb, teardown, review, fx2, xilinx, spartan 6, sram, sigrok, pulseview, dsview

Id: xZ5wKYnCNcs

Length: 46min 8sec (2768 seconds)

Published: Wed Jul 26 2017