Learn VERILOG for VLSI Placements for FREE | whyRD

so after this video you will get a clear idea how to approach your verilog syllabus and roughly in 30 days how to cover all the concepts of prelog and also practice everything 30 days is not enough to muster very long but it is all enough to tackle any interview you're gonna face in their future and we all know the importance of verilog in digital front-end interview so if this topic excite you then please hit the like button and let's get started hey everyone so my name is rajdeep currently I am working with Intel as well ASI engineer so this video gonna be in three parts in first part we will deal with the concept the resources from where we can learn very well and in part two I'll tell you how efficiently you can practice the verilog concepts and in part three I'll give you some bonus resources and also I'll show you few the sample question which are being asked in last year this one question paper so out of this 30 days roughly 60 percent of days could be reserved for learning the verilog that is very important because when you want to answer in the interview you need to know the concepts very clearly right and rest 40 of the 30 days will try to practice our very low coding so before I start you need to know one thing that verilog is something special it is not your C plus or some other link verilog will help you to create the hardware so that means coding would be little bit different from C or other languages but again verilog is nothing but it's a combination of two things one is your concept of coding and other is your concept of digital electronics and concept of coding is actually very basic knowledge of coding if you are not sure about those thing then please refer to this video here I explain in depth that how much coding concept you need to be a vlsi engineer you need that much knowledge only and after that you need to have have a deep knowledge of digital electronics so for the first two days we will revise our coding Concepts and those will include very basic things like ignition of variable what does it mean in coding the function the flow of control like if when loops and one thing is sure that if you haven't done any coding previously then only two days it's not enough and then probably this 30 days verilog roadmap is not for you you first need to know the basic of coding and that probably will take another 10 to 20 days probably 30 days but here I am assuming you already have done some coding at least you have written codes which use the application of function if else looping right from third day onward next three days we will exclusively devote ourselves to revise the digital electronics I am hoping you already have revised those digital Concepts earlier also so that's why three days would be enough inside that three days will cover everything which will include combinational circuits and also sequential circuits sequencer circuits are very important so we will give some more time there and in combination circuit you will have those thing your Adder multiplexer decoder and yeah multiplexer is very important there then encoder those things and in sequential the majority of thing is concluded actually by learning the flip flop if you know the exact how flip flop is implemented go forward with flip flop then JK flip flop Master Slave arrangements and how registers are built out of a flip flop then how counter or will encounter we have synchronized counter and synchronous counter a synchronous counter again very important for your interview purpose and also directly from digital question arrive right so these three days actually you are covered in your digital syllabus not very log is yet to start and also the concept of State machine that is again important generally in your written exam question from State machine are not so much popular but in your interview there would be for sure if it is a digital interview digital vlsi profile then there would be for sure some question from State machine also so five day are for revision and what we are revising we are revising our coding part first two days and then next three days would be our Digital Electronics probably three days would be little less so you can expand it up to by more two days like first seven days but after that we will devote our total focus to learn the very log and learning the way look just means learning the syntax not remembering the syntax but knowing the syntax and knowing the capability of verilog because nobody will tell you to write a syntax without seeing anything from your mind right you need to tell them the way you will approach that problem in verilog not exactly true things is not needed in vlsi placement questions we don't have any coding round or verilog that you need to coordinate and you need to get the answer in the exam in the placement exam I will show you few of the simple question there you will see you have the codes and you need to sometimes you need to tell the bugs the error of that code or sometime you need to predict the output of that code so you don't need to remember or learn the syntax but to know how this index are written and if you see a very log you need to able to get it output out so from day 6 onward we will spend our next 11 days from day 6 to day 16 and for verilog there are probably many resources in online both paid and bought free version but my one of the favorite resources from where I myself learned very long and that is nothing but the nptel lecture by IIT kharagpur you can see in the screen so for first 11 days we will cover the first 22 lecture so pilot 2 lecture and lecture are very small I guess 30 minutes is of one lecture so two lecture covering one day it's very much practical up to lecture 22 cover the maximum of the theme which generally arrive in the interview also and in the placement exam also after that we have some Advanced things so we will cover them if we have time but for now if you are spending more time in revising your digital electronics then probably you need to see three lecture a day but by day 16 your first 22 lecture of verilogue should be covered and also you need to make a nice notes of those lecture so from day 17 onward the rest of 14 days are very interesting why because there will be applying what we have learned during those previous 16 days and for practice seeing our very log so we have one online tool and that is called hdlb and that site is gold for learning very long or practicing very long let's Deep dive into it so this is your hdlb this page when you go there links are in the description so don't worry so you will have getting started verilog languages then combinational logic then sequential logic and as I told you you need to know your digital electronics to learn verilog sequential logic is the most important thing to focus on for the interview purpose but for your written exam purpose the most important thing is reading simulation this section so if we go inside this section then you can see something wonderful there and why it is wonderful because in the beginning one two year probably every VLS engineer who have been appointed as RTL design engineer or whatsoever in the front end they do this work only reading a very low code observing the bugs reading the simulation and proposing a solution or solving that bug so here you can see we have many topics so if I go to mask the most easiest one so they have given one of the code and the question is that this Multiplex doesn't work probably your manager will tell in a meeting this is not working you need to fix it by today and that's that's the work for beginning uh one two year you need to do and maximum people doing this thing only like observing the thing design and proposing a solution so here if you know the concepts of a log which we have learned in first 16 days or from the first 22 lecture then you can easily find it out here is that uh the last line is the is creating issue here actually because see your A and B are of 8 Bits but the out is of not of 8 bit it is of it is of one bit only so without modifying it if I run it like let's submit and let's see what its output show us and it sometimes takes some time some 30 second or 40 second and after that you can see that a student status is incorrect we know already is incorrect and they already have given us if you know the concept of multiplexer then you can see select actually manipulate your output if select is 0 probably it will select we this reference line is actually the correct answer and yours output is z means High impedance because we are doing something wrong and that's why we are getting this one so our task is that we need to modify this very low code to get this reference answer so can we do that and answer is yes if you have learned your regular Concept in first 15 days then you can easily do it and to do it is is easy actually because our output is of zero bit so we will make it off 7 bit so that's uh sorry 8 bit so the 8 bit should get the 8 the 8th bit of a or eight bit of B and this thing we need to continue for other beads here so let me do it quickly and here we have the answers so probably now if I submit should get a right status so let us check finger crossed we are getting a error and probably because see here we are defining out as 8 bit but when we are defining it we are defining it as the one bit only so here we need to change it to and this thing like I am writing here because I have already learned the very log that's why and this thing are very very easy actually whenever you go through those 22 lecture it would become a cakewalk for you and see here again syntax is wrong because this thing should come before this one and these things are okay one two time you'll do wrong you can uh see this uh error and you can guess out was the true answer and probably we need a comma also here probably I'm also not sure let's submit it and let's see we are getting an error and if we observe our error then the t is uh we are getting a when a should be B so I got the answer actually what we are doing we are uh doing wrong here actually this should without a tilde because tilde is work as inverter and this thing if you are not getting now you will get it by practice so not of worry here just you need to focus on your first 22 lecture by first section days and from 17 days things would be great so let's submit and I'm sure that I'll get a correct answer this time finger crossed again and see status is success and here you can see our our result and references are exactly similar so our mismatch is zero so by this way you can get very deep into your verilog and here uh like last 14 days only we have probably you can manage to do only 20 practice and those 20 practice are all enough this practice if we get time then we will probably do the other rest of lecture remaining there from lecture 23 to lecture 41 probably up to 41 it's not so important but I will strongly recommend you please finish up to 30 lecture for sure so now for the people who don't have time who have some other thing to cover then will work for them sure short Digital Electronics you need to cover right for your exam you need to cover that one programming again you need to do because there are some questions from C so these two thing actually they are independent of very long if you want to learn verilog or not there are two things you need to cover to get a good Mark for verilog you just cover in 10 days only the first 22 lecture of that nptel you can see it in 1.5 x of speed and after that just spend one two days to see the previous year questions how to get the previous year question check the description there I'll provide you few of the resources from here you can get the previous year VL uh previous year question and you can practice from there directly and for quick reference you can see this side and that is called your Asic world and there we have actually very uh not so much like not many question but some good example like which type of questions are or will come in your exam in your placement exam or in your interview probably in interview they ask the conceptual question like what is blocking non-blocking statement data type we have in very low like those questions but in exam this type of solution oriented question arrived there so don't forget to check the description I'll give as much as resources I have and your responsibility is to share those resources or this video with your best friend best buddy or your best mate now the bonus resources I have and that is not for the people who have their placement exam right now in one or two months but if you have time then don't forget to visit this quora profile and this quota profile is really amazing actually this is by Mr palash and he has written a few of the great answer in and around very log and he also have some strategy like how you can learn to code very log in 30 days and he have some other approaches so you can follow that approaches also and in some of the answer he also suggested few of the books which you can refer to learn verilog or in other words expertise the video log because reading book will take time so if you are in your third year or you have six seven month and you want to learn very long perfectly then you can refer one of those books so I'll also pin his profile to the description and one very important thing and that is in next 100 hours when you are seeing this video I'm gonna start a new playlist where I'll discuss all the important vlsi question which might arrive in your placement exam or in your interview so you have all the reason to subscribe to my channel so I hope if you manage your 30 days like this you can easily tackle any question of pre-log and that I am telling you from my own experience because I have followed roughly the same approach so in the screen you can see a few of the very low previous year question

Channel: whyRD

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Keywords: verilog tutorial for beginners, verilog tutorial, verilog programming, verilog, vlsi, whyRD, rajdeep, Learn VERILOG for VLSI Placements for FREE, Work Done by fresh VLSI Engineers, vlsi design, vlsi engineer, design automation, front end, rtl coding, Fresher at vlsi industry, Fresher vlsi job, semiconductor industry, Must know tips for a VLSI fresher, work life balance, frontend, digital, switch domain, validation, verification, vlsi domain

Id: vRSY6S03EFg

Length: 16min 38sec (998 seconds)

Published: Sat Oct 08 2022