Inside the Intel 4 Process and Foveros Packaging for Meteor Lake | Talking Tech | Intel Technology

welcome to talking Tech I'm your host Alejandra ojus and I am very excited as today we're here in Malaysia at an Intel Spang assembly and testing facility in which we're going to learn about the different technologies that involve video [Music] link right now we're in the middle of our journey of five nodes in four years and uh when Pat came back 2 and a half years ago uh he put in place this plan of for technology leadership catchup and that's the five notes in four years so step one was Intel 7 uh step two was Intel 4 and that's where we are today so if you look at Intel 4 you know our goals were first uh area scaling so if you look at our standard cell library and you compare it to the Intel 7 node we're able to achieve 50% area scaling or 2x area scaling however you want to describe it uh that was you know the continuation of B's law second goal of uh Intel 4 um was power efficiency right we want to deliver a lot of performance but it needs to be efficient performance some of that we get from the scaling and a lot of that we get from the transistor improvements that we Implement as well and our goal really is to take take most advantage of power efficiency when we drop a gate contact um you know prior to 10 nanometer uh you would never put it on top of a gate it was always off the gate uh and then You' use the the conductivity of theate gate metal to get to the transistor starting on 10 we dropped it on top of the gate and that that allows that um because we don't have to drop the contact so far away we can achieve better scaling so is like you're reducing your area right cuz now you have to put it outside it's directly on top so L area so yeah exactly it's you know contact was sitting out here uh here's the gate contact sitting out here and then I can drop it right on top of it so then I can you know I chop the Cell at the at the edge now we also were're able to pitch scale both the fins and the gates euv lithography was a big part of that euv lithography really allowed us to reduce some of the complexity that had grown over the years because we didn't have lithography capability of the resolution that we needed we've been able to reduce complexity and reducing complexity allowed us to achieve better yields um it's allowing us to uh run the Fab faster the metal stack is is 18 metal layers now we have a z metal layer then we have metal 1 through 15 and then we have these giant metal distribution layers up at the top so it's 18 tall you're also challenged by electromigration right electromigration is when you're putting you know voltage or power on a on a wire uh sometimes that that metal wants to move you know and and metal moving is not a good thing no um so uh you know we we developed what we called enhanced copper by doing implementing this new type of wire con stop connection you have also reduced the RC or the impedance on on it so making it yes yes uh yes uh resistivity on those lower metal layers um if you compare resistivity or uh the conductivity improvements that we have in metal zero metal one compared to uh Intel 7 it's a significant Improvement five NOS in four years so so uh Intel 4 is Step number two and we're in production today uh step number three is Intel 3 and Intel 3 will build upon Intel 4 uh it'll offer uh denser libraries for uh for scaling it'll provide additional performance opportunities uh Intel 3 is a a node that we will use for very long time for both internal and uh Intel Foundry products uh so it's pretty exciting yeah yeah step you know two done three to go fos is what we call um 3D Advanced packaging and by 3D it means we're stacking um dye on top of or silicon on top of other pieces of silicon um I think one thing that fos um is kind of a first versus the um like some of the other 3D packaging in the industry um is that we do have the capability to stack a two active die on top of each other and we can also stack a active die on top of what we call a passive die on meteor l for example um we have multiple um top Dy and we put them on a single base D and that base D serves mainly to interconnect all those dye so we could take all the D instead of building them on se you know one large die we break them into smaller functions and then we connect them um with packaging you know traditionally we do what we call um organic Flip chip packaging where we take a monolithic D and put it on a substrate um you know and then on like Raptor Lake and Alder Lake going all the way back to Haswell we put the the the platform controller PCH on the package and we we connected those together with um what we call on package IO and for example those connections between the I and substrate are like 100 microns apart we call the pitch right when we go to fos you know those those connections between the Dy and the wafer they're at 36 microns since we're talking in area it's about an 8X increase in the amount of um interconnects that we can get per millimeter so you know you need that amount of signaling between the two die um also fose it gives you know the the characteristics in the base die um it it allows those signals to be carried at very um very high bandwidth um and very low power and as we said earlier very low latency so with the technology you get the electrical characteristics you want and that allows you um to you know then partition into many different tiles so fos if I understood correctly you can correct me if I'm wrong is we have this base wafer in which we have other tiles that come on top of it so can you tell us a little bit more about that and and how is it assembled sure that's exactly right um we actually start with all the all the all of them in wafer form um we have a Bas wafer um and then we have all the top tiles come to us in Wafers um some from um internal like our compute die uh on Intel 4 um and then the other you know other D that come from us from external Foundry um we bring them in uh all the top D we take through what we call die prep or singulation so we'll cut up the die um singulate the die and then we'll send them um to sort my role as a factory manager I take care of the entire Factory op operation managing all the operation indicator to ensure operation excellent at the same time to ensure that we meeting the cost Target as well as ensure all new product introduction and release on time for meic uh we have the unique Tooling in assembly and unique product tooling that needed to uh develop partnering with TD to make sure that this run well for meteoric product alone yeah so the challenges is really how do we develop the latest tooling that enable metol at the same time ramp up fast and start up fast to make sure that we meet the due date and the committed timeline bang assembly task uh is the backend processes to assemble uh the D into the packages as well as tach the unit before finally shipped to custom we actually improve what we call known good die um so you get you know something like a you know 3 to 4% Improvement in known good Dy going into um uh going into the package so if you think about that when you're putting three or four Dy together in a package if you know that say for example they're 99% known good die because you tested them so well versus 95% known good die on wafer sort which is still really good um but you just didn't have the same coverage you know that multiplies out and by the time you get the final class test there's a you know a 10% yield difference after we sort them or singulated die test them that's where we move to kind of the first step of the fob operations this is what we call wafer assembly this was you know the major new capability that we had to put in um obviously we have to have um tools and equipment to take and processes to take the the top D and to stack them to the bottom die so we do that the bottom die or the base die is in wafer form when we do that and uh the wa for assembly flow it's kind of unique that it's a combination of both what we call like classic assembly processes and classic Fab processes so for particularly for molic molic is a Fus product so where uh DMO which is called uh Advanced packaging Fab will be doing the wafer level assembly in terms of connecting uh kind of attach of four dice on top of the base D so for ATM we will receive the F warus diet and we will do assembly which is uh D attached or chip attached attached the forus die on the substrate and the packages we stack all the die on the under the wafer um uh and then take it through the flow we then singulate um or or chop up that um that particular um die into what we call the die Stacks or the F Stacks um after that um kind of circling back to that singulated die test we do have the option to test them again since we we are able to test at the Die Level we are able to test at the die stack level and I think this is a big Advantage uh you know sometime you know there is a cost for adding a test step so we have to use it judiciously on meteor Lake um we are we've been using it through development and sampling to make sure we have a healthy process um and then we'll evaluate how we use it in hm in high volume manufacturing but it's still good to as a quality monitor making sure that the line is running well U before we send the dieet to package assembly uh once we do the uh attach we'll go through all the assembly process step whether it's epoxy as well as the uh stiffener attach then we will go to test for completing test before uh going to the Finish operation uh to do a vure check and marking and before ship ship to customer I think the one thing about um you know test not necessarily just for fos um but our you know again we have world-class backin test capabilities all of our test platforms are have been developed um inhouse over the past you know decade or longer we can do this in a very you know you know manufacturable way where we're not adding a lot of test cost and test time but still able to achieve that worldclass DPM you know and from there pack it and jip it so and that's what we're doing now I mean meteor Lake we finished all the qu samples um they are out the door this summer production materials in the line uh the line's running pretty healthy we're at our yield targets um you know reliability manufacturability targets you know we're we're we're there or really really close so yeah we're ready we are very proud to be part of this uh Journey uh to be able to enable the meteoric uh forus packages and Intel 4 uh note right so that is yeah we all super proud and to be able to be part of this CH as you can see medor Lake from an architecture point of view and also from a product point of view has a lot to offer from new AI new graphics new process technology a completely new type of architecture when we go from monolithic to disaggregated brings a lot of new features thank you for watching with us and please stay tuned for more videos that we coming your way [Music] a

Channel: Intel Technology

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Id: 7QCNBtF1JCA

Length: 11min 51sec (711 seconds)

Published: Thu Nov 02 2023