Infineon: How to choose gate driver for SiC MOSFETs and Sic MOSFET modules

welcome to the web-based training about the gate drive design cookbook for silicon carbide MOSFETs and silicon carbide MOSFET modules you can find the buttons next play again and pause in the navigation toolbar silicon carbide MOSFETs bring a lot of opportunities to power electronics however to make the most of these devices hardware and firmware design engineers have to be aware of their most important characteristics they should ask themselves how can I achieve sufficient system benefits by using silicon carbide MOSFETs let's introduce you to the learning objectives by the end of this training you will know how to calculate a reference gate resistance value for your silicon carbide MOSFET identify suitable gate driving ICS based on peak current and power dissipation requirements and find out how to fine tune the gate resistance value in laboratory environment based on worst case conditions this training into three sections first we will give you some background information about silicon carbide MOSFETs then you will see the step by step process of the gate driver IC selection and finally we will show you an example for the calculation flow before going two details on silicon carbide MOSFETs it is important to go back to the basics and show you some background information on this topic stay tuned did you know that silicon carbide MOSFETs are fast switching devices they can reach 50 volt per nanosecond or even more therefore the timing of the control signal is crucial please be aware that when we talk about an IGBT dominated working environment it is important to bear in mind that each millimetre if the PCB track has a strong influence on the MOSFET switching performance due to the high di by DT of silicon carbide MOSFETs and that in a mosfet driven working environment you have to take the higher DC link voltage ease into consideration these lead to a longer exposure of the gate driver I see two common mode transients this will subject the gate driver IC to higher common mode transients another important characteristic is that the body diode of the silicon carbide MOSFET has a much lower reverse recovery charge compared to conventional silicon diodes due to a freewheeling body diode with little reverse recovery charge nevertheless the body diodes forward voltage is quite high when compared to silicon diodes silicon carbide MOSFETs also require a relatively high gate source voltage to achieve good on state resistance and fast switching furthermore they may also need a negative gate voltage to reliably stay in off mode thus the gate voltage range is wider than for silicon MOSFETs and did you know that silicon carbide MOSFETs are also characterized by their short circuit capability which is reduced when compared to IGBTs please make sure that your selected gate driver circuits and I C's support all these silicon carbide mosfet device characteristics now we are ready to move on to the design process of the gate driver circuits let's go the selection of relevant components in a gate driver circuit is usually an iterative process this process commonly starts with first assumptions and then goes through the optimization of the circuit by fine-tuning particular items the following design steps may be fully iterated or partially iterated until the final selection is done there are four major design steps to obtain a reliable gate driver design the first step is to select the peak output current capability of the driver I see the starting point is the datasheet of the power transistor that will be driven the device performance presented in the datasheet is a best-case reference with a highly optimized gate driver layout but it is generally a good starting point the result of this phase consists in obtaining the required peak output current value for the gate driver selection since an application frequently has different operating conditions compared to those given in a silicon carbide mosfet datasheet the second design step is the adaptation of the gate resistor value to the application conditions the third step is the calculation of the expected power dissipation of both gate driver IC and external gate resistor these calculated values have to be compared to the maximum allowable values of the IC and the resistor in the datasheet it is important to look out for the gate resistors peak current capability Thermal D rating has also to be considered for both the gate resistor and the gate driver IC the last and most important design step is the validation in the laboratory this validation provides insights on whether the gate driver circuit is powerful enough to drive the power transistor and whether the power dissipation is within the limits defined in the datasheet if in the fourth step the results are not as expected iteration loops can occur for recalculation or testing of another gate resistor value as soon as the final value is defined the corresponding gate driver can be considered an option due it's performance sometimes a gate driver with a smaller peak output current may be selected for price reasons its performance in the circuit has to be evaluated again in the lab of course because a gate driver I see with less peak current capability will have a larger power dissipation let's now explore some topics described in each design step as already mentioned the first design step in the gate resistor selection is to identify the gate current required by your silicon carbide switch in order to do this we use the simplified formula shown here keep in mind that this formula ignores the internal resistance of the selected gate driver a good starting point for the identification of the gate current is to aim for the same gate current used in the switching characteristics of the datasheet the peak gate current IG can be calculated as the ratio between the gate driving voltage swing provided in the datasheet delta vgs datasheet and the resistance in the current path the external gate resistance RG datasheet used in the characterisation measurements can be extracted from the datasheet switching characteristic section it is generally specified as RG the internal gate resistance of the power transistor RG int can also be found in the datasheet as a typical value this is device and package dependent and cannot be adjusted by the end user delta vgs datasheet can be calculated as the sum of the absolute values of the on state gate voltage vgs on and the off state gate voltage vgs off the on state gate voltage is the voltage used in the datasheet switching characteristics measurements to turn on the selected silicon carbide transistor the off state gate voltage is the voltage used to turn off the silicon carbide devices according to the same datasheet measurement at this point the calculated Peak gate current IG can be used to identify a possible suitable gate driver for your application the selected gate driver should have a typical output current value equal or bigger than the calculated value in the second design step the peek gate current should be kept constant in order to allow your application to show the same switching characteristics and speeds provided in the silicon carbide switch datasheet therefore the equation can be adapted to your application conditions and to keep the same peak gate current we can adjust the variable parameters the internal gate resistance is constant as this is device dependent delta vgs in turn depends on the application and it usually has a fixed range of values as it is based on the selected power supply voltages the easiest way to keep the peak gate current constant is by adjusting the external application gate resistor RG application then the formula can be rearranged as shown delta vgs application is the swing of the gate voltage supplied to the switch and is formed by the sum between the absolute value of the positive supply voltage of the gate driver VCC 2 and the absolute value of the negative supply voltage Vee 2 used for the gate driver the following circuit exemplifies a gate driver with a ground pin GND 2 and a negative supply pin Vee 2 this happens because a negative gate voltage is recommended for silicon carbide MOSFETs to ensure that the device stays turned off during the operation of the power converter however it is not always the case that the gate driver has both pins ground and negative supply pins when this happens the negative supply voltage is connected to terminal g ND 2 and the zero volt is biased by using capacitors there are variations in the naming of the pin which should connect to the lower power supply rail sometimes instead of the Vee 2 marking on the pin GND 2 has been used unless both pins are present on the package they can both be used to connect to the lower side of the gate driver power rail at this point the power dissipation PD can be calculated note that the calculations shown are simplified assuming that the power losses during switching are only dissipated in the output stage of the gate driver this is not the case in reality because the gate resistances also take over some of the losses the proposed assumption is therefore on the safe side the power dissipated in the gate driving circuit is a function of the gate charge in the application the switching frequency and the voltage swing of the gate driver output the application gate charge can be extracted from the gate charge diagram in the silicon carbide switch datasheet first the turn on and turn off voltages are observed on the diagram y-axis it may be necessary to extrapolate the curve linearly if the visible range is not sufficient then the gate charge of the application can be calculated as the difference between the on state gate charge and off state gate charge afterwards we can calculate the power dissipated in the gate driver circuit if we know the target switching application and the supply voltage for the gate driver a linear D rating of the power dissipation has to be considered between the test condition point of PD out and the maximum Junction temperature the result should then be smaller than or equal to the absolute maximum power dissipation PD out in the output side of the gate driver at this point the main components in the gate driver circuit silicon carbide devices gate driver IC and in the gate resistor value have been selected and the design should be verified in the laboratory as mentioned in the last design step lamp of measurements are necessary to prove that the assumptions and calculations result in a safe switching of the silicon carbide transistor the review of the measurements can lead to an adaptation of the calculated gate resistor RG in general three basic tests are recommended the first test is related to the validations used to prove the absence of parasitic turn on triggered by DV by DT under worst case conditions note that worst case conditions for this test are the operations under lowest application temperatures lowest drain current and the worst case gate source voltage of the application the second test is the measurement of the gate driver IC temperature during steady state operation here it is easier to use an infrared camera although thermocouples can also help evaluate the ICS temperature and the third test takes into consideration the validation of the gate resistors loading an infrared camera can help in getting the heating of the elements furthermore the peak power of the resistor should also be calculated and checked against the single pulse rating of the resistor as given by the supplier some suppliers even provide a repetitive pulse rating diagram which can be a big help for higher switching frequencies let's find out more about each test as previously mentioned the first test is about parasitic turn on triggered by DV by DT in this figure you can see a simple gate driving circuit with a silicon carbide power device a gate driver output stage and an external gate resistor keep in mind that parasitic capacitances are always present and should not be ignored in case a transient voltage occurs between drain and source terminal there will be a displacement current through the reverse capacitance CR SS and the input capacitance C is s this leads to a temporary voltage increase at the gate node in the power transistor moreover the silicon carbide MOSFET can turn on when the voltage at the gate is at or above the gate source threshold voltage note that the gate resistor should be adjusted to mitigate this either through the design of a different gate resistor for turn on and turn off separated by a diode or by using an active Miller clamp parasitic turn on should never occur a good way to validate this is by using the double pulse test this test should be performed comprising all the conditions that may affect the gate driving circuit such as high and low drain currents which means zero current and nominal current high and low temperatures the operating temperature is varied between the maximum and minimum temperature the application is going to be submitted to nominal gate voltages in order to ensure that the selected driving voltages are appropriate for the application and both highside and low-side switches should be tested in order to ensure that neither of them has a negative influence on the other the measurements should be done directly on the silicon carbide transistor terminals or as close as possible to avoid measurement artifacts here we have an example of a parasitic turn on which at first look would be neglected and associated with the reverse recovery of the anti parallel diode the first current spike observed in the current waveform is the reverse recovery current of the upper diode d1 this is a normal behavior and can vary in shape and size depending on the dimensions and technology of the diode the second spike is the parasitic turn-on of the complimentary switch q1 as a result of the fast DV by DT generated by the turn-on of q2 the parasitic turn-on can also be observed at zero current switching where interferences from other current flows are not present here you can see an example of a parasitic turn-on that at a first glance would be masked by the capacitive discharge the first spike is the capacitive discharge and it is considered a normal behavior the second spike is the parasitic turn-on of the lower silicon carbide switch q2 this is again a case of a transition with zero transistor current here the lower side transistor is switched on the first spike observed is the gate current that is used to turn on the lower silicon carbide MOSFET q1 the second spike is the parasitic turn-on of the upper switch and zero switching current parasitic turn-ons result in increased losses in the half bridge and in early degradation of silicon carbide devices or in extreme cases even in the destruction of the power transistors by increasing the gate resistor value the transistor switching speeds can be slowed down and the DV by DT in the circuit will be reduced similarly by choosing a smaller gate resistor value the silicon carbide transistor is switched faster and higher DV by DT transients are generated in the circuit at this point we have adjusted our gate resistor and confirmed that no parasitic turn on is taking place let's move on to the other test the next step is to prove that the power losses in the gate driver are not higher than expected and that the junction temperature is kept within the absolute maximum limits the case temperature can be measured during thermal steady-state operation in order to ensure that the chip reaches its operating temperature note that this should ideally be tested under expected operating ambient temperature the easiest way is to record the case temperature with a thermal camera if this is not an option a thermocouple can also be used making sure that the case temperature is properly measured now the junction temperature can be estimated using the following formula based on the calculated power dissipation and on the measured case temperature note that the case temperature can be obtained from the thermal measurement and that the thermal coefficient Junction to top is given in the data sheets of the selected Infineon gate driver ICS afterwards the junction temperature is ready to be calculated finally the calculated Junction temperature should be compared to the maximum allowable Junction temperature in the datasheet and it has to be ensured that it is smaller or equal to that limit please note that any deviation from the layout associated to the thermal resistance which is given in the data sheet can result in different temperatures compared to the calculation a room temperature measurement may be suitable as well the temperature difference between ambient and case temperature has to be added to the applications worst case temperature then the junction temperature can be calculated as described above moving on to the third test one thing that gets quite frequently neglected is the thermal stress encountered by the gate resistor after selecting the gate resistor the peak losses can be calculated this should also take the thermal D rating into consideration which is given in the individual D rating curve of the resistor type in our case the D rating is 80% due to high temperature operation at 85 degrees Celsius the peak power can be calculated based on the gate voltage swing and on the value of the resistor using the following formula afterwards the pulse limit as a function of time can be observed in the datasheet of the selected resistor this would look similar to the example shown where the y-axis shows the peak pulse power and the x-axis shows the pulse length a good approximation for the pulse length can be obtained by multiplying the product between the gate resistor value RG and the input capacitance C is s of the silicon carbide power device by five the gate resists temperature should also be measured at steady-state a good way to measure it especially if a thermal camera is used is during the case temperature measurement for the driver I see in this last section let's see a calculation flow example going through all the design steps this design example was based on an Infineon evaluation board with the following characteristics silicon carbide MOSFET positive gate voltage negative gate voltage maximum switching frequency and maximum ambient temperature the first step is to calculate the required peak gate current according to the information on the datasheet we will execute the example based on a real evaluation board with the following characteristics there are two relevant sections for this calculation the switching characteristics and the static characteristics of a silicon carbide MOSFET should be considered the basic equation for the peak gate current is Ohm's law V over R the resistance is the sum of the external gate resistor value according to the datasheet and to the power transistors integrated gate resistor value while the voltages in this specific case the sum of the positive on state voltage and the negative off state voltage but where can you find this information the switching characteristics give information about the used external gate resistor the integrated gate resistor is always stated in the static characteristics note that the value should be assumed as zero if no information can be found there and the effective gate voltages can also be found in the switching characteristics we can see there is an on state voltage of 15 volts and an off state voltage of minus 5 volt executing the initial equation will lead to a peak current of 3 point 33 amp ere keep in mind that this calculation does not consider any resistance on the gate driver IC all results in worst-case values for the gate driver IC current capability the peak current of 3.33 amp ere is the reference value for the selection bearing this in mind we can select one EDC 20 H 12 a H in the datasheet of the one II D C compact family this IC offers a typical value of 3 point 5 ampair peak current the test condition for this value is a voltage swing of 15 volt since a larger swing was used in our example the one EDC 20 will also deliver some more current than the quantity specified in the datasheet regarding the adaptation to application requirements the target application example is the following evaluation board and this is its isolated power supply circuit we can see that the output voltages are identical compared to the datasheet starting with the same equation used for calculating the peak gate current let's now calculate the external gate resistance the rearrangement of the equation for the target gate resistor results in the equations shown here the next step is to insert the values the third design step is the calculation of the icees power dissipation and its effect on the junction temperature first let's have a look at the power dissipation of the I see normally the loss is caused by the charging and discharging of the gate capacitance are dominant therefore other losses in the driver IC are neglected the gate charge losses are calculated using the total gate charge qg the switching frequency and the gate voltage swing the gate charge comes from the gate charge diagram in the datasheet in special cases the curves have to be linearly extrapolated if the diagram does not represent the used voltage swing note that it is necessary to use the qg value of the table in a MOSFETs datasheet if no diagram is given the calculations will then result in a higher dissipated power however this is on the safe side and a best can-do strategy the power dissipation is calculated with 0.126 watt as a first check we compare this number with the total allowed power dissipation at an ambient temperature of 25 degrees Celsius here you can see an infrared camera picture it is taken close to the thermal equilibrium when there is no major temperature increase to be observed anymore the graph shows the temperature curve over time of position cursor - resulting in a value of approximately 58 degrees Celsius the relative increase versus the room temperature is 58 degrees Celsius - 25 degrees Celsius equals 233 degrees Celsius this is a strong difference to the calculated increase of 21 degrees Celsius it can be explained due to the larger copper area of the reference layout of the datasheet this copper area provides additional cooling for the driver I see the real layout which we used for the evaluation board does not have such a copper area thus the temperature of the IC is higher than calculated our measurement combines the measurement of the driver IC with the measurement of the gate resistor temperature this is possible due to the close proximity of both components the next step is the lab verification the following graph shows a turn on waveform using a gate resistance of 2 ohm the black curve is the drain source voltage the red one is the source current and the green curve is the gate source voltage these conditions results in a quite high reverse recovery peak current of approximately 87 amp ere it also causes some oscillations in both the gate voltage and source current these oscillations are not desired and should be kept under control therefore a slowdown of the switching transient is needed this is achieved by increasing the gate resistor value here the waveform shows the transient when using an external gate resistor of 10 ohm they are much cleaner now compared to the previous waveform it is also possible to see that the reverse recovery peak current reduced significantly to 55 amp ere therefore the decision of the gate resistor goes for an external gate resistor value of 10 on this training you have seen that a gate driver design has to support silicon carbide MOSFET characteristics which can also include low gate source threshold voltages silicon carbide MOSFET switching behavior in the application has to be verified experimentally in the final design by lab double pulse measurements and in addition the power dissipation of the gate driver circuit also has to be verified by calculation and temperature measurements using for instance an infrared camera you have now finished this training about the gate drive design cookbook for silicon carbide MOSFETs and silicon carbide MOSFET modules thank you for joining

Channel: Future Electronics

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Keywords: Infineon, gate driver, SiC MOSFETs, Sic MOSFET, MOSFET

Id: BJBy1YIQeSg

Length: 29min 16sec (1756 seconds)

Published: Thu Jun 11 2020