We are on the cusp of a major shift in
semiconductor manufacturing. The physical form of the transistor is changing. It’s only
the second time ever that the transistor is being altered in such a fundamental way, the
last time it happened was over a decade ago. Gate-All-Around Field Effect Transistors
are not some far away vision of the future, first chips with GAA-FETs already exist and
within just a few years, every chip produced in a leading edge node will use Gate-All-Around,
promising improvements in power efficiency and performance. But just like any new technology,
GAA comes with its own unique challenges. Let’s take a look at what Gate-All-Around
transistors are, talk about benefits and challenges and figure out which process nodes
and potential products will be first to use GAA. Because you might be able to buy
GAA based chips sooner than you think. The field effect transistor has always been about
control. Control over the flow of current between source and drain. In order to exert control
over the flow of current, a gate is placed in-between source and drain. This gate emits a
electromagnetic field, which affects the empty space between source and drain, the so called
channel, and depending on if the electromagnetic field is turned off or on, the current either
flows through the channel, or it doesn’t. That’s the field effect. And that’s how the gate controls
the flow of the current. At least in theory. For many decades, transistors were designed
and build in 2D. In this transistor layout, source, drain and gate are located on a
planar space, fittingly called a planar transistor. The planar nature of this design
also meant that the electromagnetic field of the gate can control the channel from only
one side, the top. Not much of a problem, if the distance between source and drain
is large enough to allow for a large gate with a large electromagnetic field. But
as transistors got smaller and smaller, source and drain got closer and closer
and the gate also became smaller, reducing the amount of control it had over the
flow of the current between source and drain. And because field effect transistors are
all about control, losing control was not an option. The physical form of the transistor had
to change. The result was the FinFET transistor, which is called that way, because it look
like the fin of a fish. FinFET transistors raise the entire structure of the former
planar transistor into a 3D space, which allows the gate to wrap around the channel
between source and drain from three sides instead of only one. And more sides equals more
electromagnetic fields, thus more field effect and thus more control. But because transistors
never stopped getting smaller, we are now at a point where even FinFET transistors are not always
strong enough to control the flow of the current, leading to unwanted side effects like a higher
power draw. Because if a closed gate isn’t able to stop the flow of the current, even a transistor
that is supposed to be turned off consumes power. Considering the importance of the field effect
transistor in today's world, it has always been surprising to me that the layout has only been
altered once so far. From planar to 3D. But this is about to change, with Gate-All-Around
the transistor levels up for a second time. Again, it’s all about control. And the only
sure way to further increase the control of the gate over the channel between source and
drain is to control it from more sides. Since FinFETs already cover three sides, there isn’t
much room for improvement and as the names so perfectly describes, with Gate-All-Around
transistors, the gate wraps all around the channel. This means the electromagnetic
field can enter the channel from all sides, offering the maximum amount of field effect
and thus control. Even if the gate itself is very small. Which is important if we
actually want to continue shrinking the transistor size further, beyond the
current 3nm class of process nodes. On paper, GAA seems like a simple and very obvious
solution, but when it comes to manufacturing, Gate-All-Around transistors are a very different
beast. Planar and FinFETs can be manufactured with the classic semiconductor production
steps of using lithography and etching to form the physical shape of the transistors. But
because GAA-FETs include structures inside of structures - the channel is fully enclosed by the
gate - you can’t continue to just use etching as a method of production. Gate-All-Around transistors
use epitaxy, which is the deposition of material onto the wafer, to define the channel size.
Gate-All-Around transistors are basically deposited onto the wafer, instead of only
etched. Jon from Asianometry has a great video about Gate-All-Around transistors
and because he’s not only more handsome but also smarter than me, I recommend that you
check out his video if you are interested in a in-depth look at how GAA is manufactured.
I’ll put a link in the video description. But not only production is complicated,
testing is also difficult. With planar and FinFETs you could very straight forward measure
the size of your gate or fins and check if they pass your quality control or not. With GAA,
you have to measure the channel size or the dielectric material deposition that isolates
the channel from the gate in a structure, that is completely wrapped inside another
structure. Metrology, the science of measuring, has never been this important and difficult
at the same time. This increase in complexity also means that the tools to design
next-gen Gate-All-Around devices, like Electronic Design Automation software, has
to be adopted to the new reality of complex and encompassing transistors. A area where
human minds are increasingly pushed to their limits, and one of the truly exciting
applications of machine learning models. Modern semiconductors, and that literally includes
all current CPUs, GPUs and even memory chips, require extreme precision, down to a nano scale
level. This need for ultra-high precision applies to most of the process steps silicon wafers must
take in their journey through a semiconductor FAB.
One of the most important, but also difficult steps during chip production, is deposition.
ASM’s systems are designed for deposition processes where super thin films, or layers, of
various materials are grown or deposited onto the wafer. And when I say super thin, I really mean at
nanoscale. One of the technologies that makes this possible is called Atomic Layer Deposition, or
ALD for short, and I’m actually excited that ASM, the market leader in ALD, is sponsoring this
part of the video.
Every single one of you watching right now probably owns and uses products
that have been built with technology from ASM, because leading-edge foundries are relying on ASM
technology. Atomic Layer Deposition is one of the few technologies, where the name is actually
spot on, because ASM’s tools literally deposit materials atom by atom.
Since the early 1990s, ASM has focused
its efforts on deposition. In 2007, their Pulsar ALD tool became the first system used
in the high-volume manufacturing of devices using a new hafnium-based high-k gate dielectric
material. Since that breakthrough, ASM has continued to increase their footprint with leading
edge customers. They have brought novel deposition processes to the market to realize 3D device
architectures that can only be enabled by ALD.
Thanks again to ASM for sponsoring this part of the video today. if you
want to know more about the tools used to produce leading-edge computer chips, check them out at
asm.com or at the link in the video description. With a perfectly fitting sponsor like that I
really don’t need a segway. But GAA does need real world process nodes and products to show
the benefits of a gate with more control over the channel. The benefits are supposed
to be around 20-25% lower power draw, 10% higher clock speeds and up
to a 15% increase in transistor density. The exciting part is that all three
leading foundries, and that includes TSMC, Samsung and Intel, either already have
GAA process nodes ready or are very close. This time, Samsung was first, with their Samsung
Foundry SF3E node. Unlike with TSMC, the “E” in a Samsung node doesn’t stand for “enhanced”,
but for “early”. And it was a very early node, the first one with Gate-All-Around transistors.
You can think of it as a kind of pipe cleaner, to iron out the kinks. SF3E was low volume but it
did produce real chips. According to TechInsights, MicroBT produced its “Whatsminer M56S++” crypto
mining chips in SF3E. Crypto mining chips are relative simple, at least compared
to much more complex ASICs or SoC, and contain very little SRAM cells, which
makes them perfect for early production runs. But Samsung isn’t stopping there. The
follow up SF3 node, which dropped the “E”, had its first tape out just a few weeks
ago. All we know from the press release, which was done in cooperation with Synopsis to
bring home the point that advanced EDA tools are needed to design advanced Gate-All-Around
transistors, is that the chip in question is a “Flagship Mobile CPU with Leading Performance”.
I’m actually very interested to see which company is behind that product, leave your best guesses
down in the comments. There are plenty of options. From SF3 on, all following Samsung process
nodes will use GAA transistors and I’m sure it won’t be long until we see plenty of
products based on this new technology. As I said in the beginning of the video, GAA
isn’t in the future, it’s already here. Next in line is Intel and this is a very
interesting one, because GAA isn’t the only new technology Intel is introducing with
its next-gen process nodes. I’ve already made a in-depth video about Backside Power
Delivery on Intel’s 20A and 18A nodes, but these nodes will also introduce RibbonFETs,
which is how Intel calls their GAA transistors. 20A is Intel’s in-house node and the
first available product should be some upcoming Arrow Lake mobile variants.
I’m honestly looking forward to this, because with GAA and backside power, Intel could
have a truly great process node on their hand. In 2025, 18A will follow, most likely with Panther
Lake. And if 18A is as good as Intel claims, we might see plenty of other, non Intel chips,
produced in 18A by Intel’s new foundry business. Last, but certainly not least, is TSMC. TSMC
is a bit more conservative in their technology roadmap. GAA transistors will be introduced with
the next-gen N2 product family, while backside power delivery will follow at a later point
with A16. TSMC calls their GAA implementation “nano sheets” and if I had to guess, I’d say
that it’s very likely Apple will be the first customer using TSMCs N2 node with Gate-All-Around
transistors, maybe as early at late next year. As you can see, all three leading foundries are
very close when it comes to the introduction of Gate-All-Around Field Effect Transistors into
their process nodes. Samsung has a slight head start with SF3E, but their non-early SF3 node
just had its first tape-out very recently. Intel is on a similar timeline. With a potential
Arrow Lake mobile on 20A early next year, we could see products on the shelf's in a similar
time frame. And even tho TSMC is a bit behind, depending on when N2 mass
production starts next year, a potential iPhone 17 SoC could already
be based on N2 in the fall of next year. It’s not often that the physical layout
of the transistor changes. To be precise, GAA is only the second time since the
invention of the field effect transistor as we know it. The first FinFET based product
was Intel’s Ivy Bridge back in 2011 and while it offered a reduction in power draw, the
true benefits of FinFETs were only revealed in the following generations. Since then,
the FinFET transistor has not only matured, but become the dominant transistor
shape in modern semiconductors. It’s very likely a similar story with
Gate-All-Around. While first generation products should offer great benefits, the true
capabilities of GAA will only be revealed with upcoming process node generations. But it’s a
exciting time to be a fan of semiconductors. Because while others already proclaim the death of
Moore’s Law, the technological innovation is only starting to ramp up. And Gate-All-Around
will play a major part in that journey. What comes after GAA? The thumbnail of this
video already teases a potential post-GAA future. In the picture you can see the result
of forward looking transistor research done by imec in Belgium. Next to the nano sheet GAA
transistor, we can see a so called fork sheet transistor. Again, a very descriptive name, one
of the reasons I love semiconductor technology. I hope you found this video interesting
and see you in the next one.
