- Hey, everybody, welcome
to Altium Academy. I am your host, Zach Peterson. I'm also a technical
consultant for Altium, and today, we're gonna be talking about decoupling capacitor placement. So do you know where you should place your decoupling capacitors? 'cause there is still a longstanding myth going around that you
should just kind of place some randomly wherever
you like along the board. In the past, that used to work fine. There are reasons it
doesn't work so well today and that's what we're gonna look at. So let's go ahead and get started. (upbeat digitized music) So if we get started by looking
at the top layer of a board, we can initially just kind of look at where decoupling capacitors
were typically placed before the days of high speed and where it might be okay
to continue placing them if you're not dealing
with a lot of high speed or even high-frequency stuff. Typically, what would
happen is you'd have like, maybe a power section over here. You'd have your power connector or maybe you'd just have a couple of solderable pads or something like this, and then you might have
kind of a big section of decaps over here in the corner. Maybe they would be spread
around out around the board, but not really targeting
any specific chips, and then you would have
a lot of digital logic in different components
all over the board. So maybe your, you know,
main controller was here, maybe this is your MCU, and then you have some other peripherals kinda scattered around the board. Whether or not they need
decoupling capacitors, it depends on what the chip
actually is meant to do, but typically, what would happen is you'd basically just
kinda put all the decaps in this one area and then
people would start to wonder why they start to get
low-frequency EMI failures, and the reason they would start getting these low-frequency EMI
failures is because the decaps were not properly targeting
specific chips that need power when they start switching
and sourcing digital signals going to other peripherals in the board. Now, when I say targeting
a particular chip with a decoupling capacitor,
what does that mean? Well, it's all about where you place it and where you place the
decoupling capacitor matters and we've talked about
this in previous videos relating specifically to parasitics. If you don't put the decoupling capacitor in the right place, you will get excessive parasitics that can interfere with power delivery and if you don't have good power delivery or good, stable power
delivery, I should say, then you could notice power
fluctuations on the power bus and you could also notice
noise on the I/Os coming from your main chip as those
logic circuits start to switch. (gentle music) So where should you put
your decoupling capacitors to ensure that you have
stable power delivery? Well, you should put
them closer to the pins that you actually want to decouple, and I'll explain why
that is in just a moment, but first, it kinda helps to
look at where they would sit in the actual PCB layout
in relation to the package. We just kinda draw out an
integrated circuit package. Maybe we've got some pins here and we've got identical pins down here. Typically, what you'll see
is like, this is your VDD. This is your core voltage and then here you'll
have the VSS or ground. Same thing down here. You might have VDD here or maybe it's a different rail. Here, you'll have VSS or just ground and so if we're gonna place
a decoupling capacitor here, we would ideally want it
to essentially just bridge these two perfectly. So we would basically have our cap here and then it would go right here. So typically, you won't just
have one decoupling capacitor although depending on
the size of the chip, sometimes you can do just fine with one as long as the chip
isn't running too fast. So you could have just one here or you could have two in parallel and you would essentially
wanna put them pretty close to each other, and so the idea behind
putting these very close to the VDD and VSS pins is that you have as small of
a loop area here as possible and essentially to do that. (gentle music) So this is one way that's okay to do it. Another way that's
probably better to do it is to actually put these on the back layer and then feed these into the power rail on the top layer and then the ground plane on the very next layer through vias. Now, the challenge with
that is, of course, if you are doing that, you
could create a lower limit on the inductance because of
the inductance of those vias. So there will always be
some loop inductance here between these two pins
passing through your caps and then coming back
into this other pin here. So we have some discharging
current that flows into this IC whenever any
of the I/Os start switching, and we'd like to ideally
minimize the inductance along that path to ensure that we have the fastest possible response between these capacitors to provide power into this chip when
the I/Os are switching. In order to do that, if we
put it on the back layer and we put it in through vias, again, as long as we're not dealing
with two fast circuits, then we can usually get
away with just one or two, possibly a few more in
order to provide the level of decoupling needed to
give this chip enough power so it can run stably and
we'd do the same thing here. We would basically have a cap. It could go into the ground plane on the next layer with a via over here and then it could go right up to the rail. Let's say we're routing, you know, power on the top rail here over to VDD. You could feed that directly
into that rail through a via. So if this is on the back layer, all this is on the top layer and that provides a nice, tight loop for your current to then try and minimize any of that inductance that you would add based on
the location of this capacitor. (gentle music) So what happens if we
were trying to provide stable power to this chip, but we started putting our
caps all the way off here in random places? Well, now, we've got very
large return loops here for all of the current that
gets discharged from both ends of this capacitor and then
flows up here to VSS and VDD. So instead of this, let's just
suppose that we have these. Well, now, our current loop associated with this discharging current reaching these two pins is much larger. Same thing here. If we have, you know, a cap down here, it has actually a much larger path that it has to flow through in order to provide stable
current to this chip. Now, if this chip is
switching very slowly, maybe it's not even switching repeatedly to provide a bit stream. Maybe it's just switching very slowly to maybe source some configuration signals to another chip, let's say. Well, then this may not be such a problem because even though you're
adding some inductance here, the issue is that you're
not switching so fast that you're gonna excite a transient that could then create oscillations on the output from the I/O when this chip starts switching. When they're farther away, only appropriate when you have, or they're only going to
be able to source current when you have very slow switching signals coming off of this chip. When it's running at higher
speeds, as is typically the case with modern chips that are
using like an SPI bus or faster, then you would wanna bring these closer to the VSS and VDD pins, and that would apply to all of
those pins around the board. So ideally, you'd wanna try and get 'em as close as possible. Probably, the easiest way to do that. If I just look on the
back layer, let's say, I would literally just
wanna say, put this cap down here and maybe put the other ones or any of the other ones right next to it, and then I could just
route those through vias up to the ground plane on the next layer and then down to any power plane or power rail on the next layer over here. So this is not a bad way to do it. (gentle music) Now, what happens if you have
something much more dense, maybe it's not a package like this where you've got all the
pins around the outside, like, you know, a QFN package
or something like that. Maybe it's like a BGA. So with a BGA, you're gonna
have really high I/O count. You're also gonna have
really high pin counts for ground and power. Where do you put the
decoupling capacitors then? Do I wanna put 'em off here somewhere and try and route 'em in? Do I wanna just put 'em around the chip and then try and connect
'em all to the planes or is there a better way to do it? To maybe see a better way to do it, let's take a look at an example. Okay, so what we're looking
at here is the schematic and we've got two rails here. There's actually multiple
rails in this project, but I just kinda wanna focus on these ones here for just a moment. So if you look at these rails, you can see that we've got a
lot of decoupling capacitors, all placed in parallel, and the reason for doing
this is, number one, to build up a lot of capacitance, because all of these capacitances are gonna add for each of these rails and that's because the particular chip that these are being used
on needs to draw a lot of current to support a
lot of high speed I/Os all in the same package,
and this is a BGA. Now, if we just start
kind of counting here, I mean, I think you're
gonna count maybe 30 or so. I haven't done an exact count, but you're gonna count about 30 of these decoupling
capacitors in this image. So where are we gonna put
all of these around a BGA? Because we can't put 'em on the same layer and then try and route in to
all of these different BGA pins on, let's say an internal
layer on the backside. We could try and use a
plane, but the problem is, suppose I put C145 very
close to the package and then route through the plane, each of these additional
caps is gonna be farther and farther away from the BGA in order to provide the
capacitance that you need and that's gonna add inductance 'cause each of these wires is gonna have some parasitic conductance. So what we can do is if you
just look at the back layer, you'll start to see some of
those reference designators that are along this portion of the BGA. So here, we're looking
at the backside of BGA. You can see all of the vias
that are used in the fan out and then you can see some of
those reference designators here that are part of this big
decoupling capacitor network and what's going on is they're
actually connecting directly to some of the power pins that are coming off of the fan out and then they're connecting
into a ground via that goes into the ground
plane on an internal layer. So this is basically the way you would wanna do this on a BGA. This is obviously a really dense layout because you can see right here, if I zoom in, some of these
packages, they're pretty small, but they're also lying right
on top of the via hole, and so in this case,
you'd be doing via in pad and you would wanna make sure that all of these vias are plugged in order to prevent
wicking through the board, that could then possibly cause
a short on the other side. By doing this, you're getting the smallest
possible current loop path between the cap and then
the internal plane layers to then provide the
decoupling that you need in this layout to ensure that stable power is being delivered, and so just to kinda check
here, if I go back here, you can see here, C154. If I go over here to the schematic, you can see it's right
here on the 1V8 rail, and we've got several others here that are on this same rail. If we go back over here, you
can see some of those here in this portion of the layout. So this is kinda typical
for BGAs that are large and need to support a
lot of high speed I/Os. What they will do is they will
cluster a lot of the ground and power pins in the same location in order for you to make
these kinds of connections. That way, you don't have to
put these caps way over here, let's say, and then route
into an internal layer and try and line 'em up out here and then hope that you
get low inductance paths going over here to these pins, because you wanna try and
minimize that inductance to ensure that you get stable power. (gentle music) Okay, so, so far we've
been talking about power and power is an important part of this, but the other reason
that this is important is because of noise on the I/O. So a related problem is
actually called ground bounce. So we haven't talked
about ground bounce a lot, but it is actually a power problem that becomes a signal problem and it is related to the inductance along the path that
the discharging current from these capacitors will
then see as it follows through an I/O circuit
and then ends up traveling out of one of the I/Os over
to a receiving circuit. So basically, when ground bounce occurs, let's say that we have an
I/O here when this thing starts sourcing its signal, instead of having a nice clean
digital signal like this, what you actually get
is on the rising edge, you get a little bit
of noise that comes out and then same thing on the falling edge. You get a little bit of noise and so this occurs
because of the inductance along this path, not only do
you wanna minimize inductance for clean and stable voltage
to hit all these chips, but you also wanna do it to make sure that when the I/O switches,
there is minimal ringing on the rising and falling
edges of these signals. All right, everybody, so
that answers our question about decoupling capacitance and where to put decoupling
capacitors in the PCB layout. Again, don't scatter,
'em all the way around and expect that they're
always gonna be effective. Be careful about where you place them. Place them close to the power
supply and the ground pins and you will get the best possible effect both for power stability and
for stability in your I/Os. All right, thanks, everybody. If you like this video,
hit the like button, hit the subscribe button, leave your comments and questions
in the comments section. Don't be afraid to send those
questions over to YouTube at altium.com, and last but not least, don't forget to call
your fabricator, folks. (somber music)
